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vpx 3225d, vpx 3224d video pixel decoders edition nov. 9, 1998 6251-432-2pd preliminar y d a t a sheet micr onas m i c r o n a s
preliminary data sheet vpx 3225d, vpx 3224d 2 micronas contents page section title 6 1. introduction 7 1.1. system architecture 8 2. functional description 8 2.1. analog front-end 8 2.1.1. input selector 8 2.1.2. clamping 8 2.1.3. automatic gain control 8 2.1.4. analog-to-digital converters 8 2.1.5. adc range 8 2.1.6. digitally controlled clock oscillator 10 2.2. color decoder 10 2.2.1. if-compensation 10 2.2.2. demodulator 11 2.2.3. chrominance filter 11 2.2.4. frequency demodulator 11 2.2.5. burst detection 11 2.2.6. color killer operation 11 2.2.7. pal compensation/1-h comb filter 12 2.2.8. luminance notch filter 13 2.3. video sync processing 13 2.4. macrovision detection (version d4 only) 14 2.5. component processing 15 2.5.1. horizontal resizer 16 2.5.2. skew correction 16 2.5.3. peaking and coring 16 2.5.4. ycbcr color space 16 2.5.5. video adjustments 17 2.6. video output interface 17 2.6.1. output formats 17 2.6.1.1. yuv 4:2:2 with separate syncs/itu-r601 18 2.6.1.2. embedded reference headers/itu-r656 20 2.6.1.3. embedded timing codes (bstream) 20 2.6.2. bus shuffler 20 2.6.3. output multiplexer 20 2.6.4. output ports 21 2.7. video data transfer 21 2.7.1. single and double clock mode 22 2.7.2. half clock mode 23 2.8. video reference signals 23 2.8.1. href 23 2.8.2. vref 23 2.8.3. odd/even information (field) 25 2.8.4. vact
preliminary data sheet vpx 3225d, vpx 3224d 3 micronas contents, continued page section title 26 2.9. operational modes 26 2.9.1. open mode 26 2.9.2. scan mode 28 2.10. windowing the video field 29 2.11. temporal decimation 30 2.12. data slicer 30 2.12.1. slicer features 30 2.12.2. data broadcast systems 31 2.12.3. slicer functions 31 2.12.3.1. input 31 2.12.3.2. automatic adaptation 31 2.12.3.3. standard selection 31 2.12.3.4. output 33 2.13. vbi data acquisition 33 2.13.1. raw vbi data 34 2.13.2. sliced vbi data 35 2.14. control interface 35 2.14.1. overview 35 2.14.2. i 2 c-bus interface 35 2.14.3. reset and i 2 c device address selection 35 2.14.4. protocol description 36 2.14.5. fp control and status registers 37 2.15. initialization of the vpx 37 2.15.1. power-on-reset 37 2.15.2. software reset 37 2.15.3. low power mode 38 2.16. jtag boundary-scan, test access port (tap) 38 2.16.1. general description 38 2.16.2. tap architecture 38 2.16.2.1. tap controller 38 2.16.2.2. instruction register 38 2.16.2.3. boundary scan register 39 2.16.2.4. bypass register 39 2.16.2.5. device identification register 39 2.16.2.6. master mode data register 39 2.16.3. exception to ieee 1149.1 39 2.16.4. ieee 1149.1?1990 spec adherence 39 2.16.4.1. instruction register 39 2.16.4.2. public instructions 40 2.16.4.3. self-test operation 40 2.16.4.4. test data registers 40 2.16.4.5. boundary-scan register 40 2.16.4.6. device identification register 40 2.16.4.7. performance 44 2.17. enable/disable of output signals
preliminary data sheet vpx 3225d, vpx 3224d 4 micronas contents, continued page section title 45 3. specifications 45 3.1. outline dimensions 48 3.2. pin connections and short descriptions 45 3.3. pin descriptions 47 3.4. pin configuration 48 3.5. pin circuits 50 4. electrical characteristics 50 4.1. absolute maximum ratings 51 4.2. recommended operating conditions 51 4.2.1. recommended analog video input conditions 52 4.2.2. recommended i 2 c conditions 52 4.2.3. recommended digital inputs levels of res, oe, tck, tms, tdi 53 4.2.4. recommended crystal characteristics 54 4.3. characteristics 54 4.3.1. current consumption 54 4.3.2. characteristics, reset 54 4.3.3. xtal input characteristics 55 4.3.4. characteristics, analog front-end and adcs 56 4.3.5. characteristics, control bus interface 56 4.3.6. characteristics, jtag interface (test access port tap) 57 4.3.7. characteristics, digital inputs/outputs 57 4.3.8. clock signals pixclk, llc, and llc2 58 4.3.9. digital video interface 58 4.3.10. characteristics, ttl output driver 59 4.3.10.1. ttl output driver description 60 5. timing diagrams 60 5.1. power-up sequence 60 5.2. default wake-up selection 61 5.3. control bus timing diagram 62 5.4. output enable by pin oe 63 5.5. timing of the test access port tap 63 5.6. timing of all pins connected to the boundary-scan-register-chain 64 5.7. timing diagram of the digital video interface 64 5.7.1. characteristics, clock signals 65 6. control and status registers 65 6.1. overview 68 6.1.1. description of i 2 c control and status registers 72 6.1.2. description of fp control and status registers
preliminary data sheet vpx 3225d, vpx 3224d 5 micronas contents, continued page section title 83 7. application notes 83 7.1. differences between vpx 3220a and vpx 322xd 83 7.2. impact to signal to noise ratio 83 7.3. control interface 83 7.3.1. symbols 83 7.3.2. write data into i 2 c register 83 7.3.3. read data from i 2 c register 83 7.3.4. write data into fp register 83 7.3.5. read data from fp register 84 7.3.6. sample control code 84 7.4. xtal supplier 85 7.5. typical application 88 8. data sheet history
preliminary data sheet vpx 3225d, vpx 3224d 6 micronas video pixel decoder release note: this data sheet describes functions and characteristics of vpx 322xd?c3 and d4. revi- sion bars indicate significant changes to the pre- vious edition. 1. introduction the video pixel decoders vpx 3225d and vpx 3224d are the second generation of full feature video acquisi- tion ics for consumer video and multimedia applica- tions. all of the processing necessary to convert an ana- log video signal into a digital component stream have been integrated onto a single 44-pin ic. moreover, the vpx 3225d provides text slicing for intercast, teletext, and closed caption. both chips are pin compatible to vpx 3220a, vpx 3216b, and vpx 3214c. notable fea- tures include: video decoding ? multistandard color decoding: ? ? ? ? ? ntsc with y/c comb filter ? two 8-bit video a/d converters with clamping and auto- matic gain control (agc) ? four analog inputs with integrated selector for: ? ? ? ? horizontal and vertical sync detection for all standards ? decodes and detects macrovision 7.1 protected video (version d4 only) video processing ? hue, brightness, contrast, and saturation control ? dual window cropping and scaling ? horizontal resizing between 32 and 864 pixels/line ? vertical resizing by line dropping ? high-quality anti-aliasing filter ? scaling controlled peaking and coring video interfacing ? yc b c r 4:2:2 format ? itu-r 601 compliant output format ? itu-r 656 compliant output format ? bstream compliant output format ? square pixel format (640 or 768 pixel/line) ? 8-bit or 16-bit synchronous output mode ? 13.5 mhz/16-bit and 27 mhz/8-bit output rate ? vbi bypass and raw adc data output data broadcast support (vpx 3225d only) ? high-performance data slicing in hardware ? multistandard data slicer ? ? ? full support for ? ? ? programmable to new standards via i 2 c ? automatic slice level adaptation ? vbi and full-field mode ? data insertion into video stream ? simultaneous acquisition of teletext, vps, wss, and caption miscellaneous ? 44-pin plcc package ? total power consumption of below 1 w ? i 2 c serial control, 2 different device addresses ? single on-chip clock generation, only one crystal need- ed for all standards ? user programmable output pins ? power-down mode ? ieee 1149.1 (jtag) boundary scan interface software support ? mediacvr software suite ? ? ? ? webtv for windows ?
vpx 3225d, vpx 3224d preliminary data sheet 7 micronas 1.1. system architecture the block diagram (fig. 1 ? 1) illustrates the signal flow through the vpx. a sampling stage performs 8-bit a/d conversion, clamping, and agc. the color decoder sep- arates the luma and chroma signals, demodulates the chroma, and filters the luminance. a sync slicer detects the sync edge and computes the skew relative to the sample clock. the video processing stage resizes the ycbcr samples, adjusts the contrast and brightness, and interpolates the chroma. the text slicer extracts lines with text information and delivers decoded data bytes to the video interface. note: the vpx 3225d and vpx 3224d are not register compatible with the vpx 3220a, vpx 3216b, and vpx 3214c family. tck tms tdi tdo resq fig. 1 ? 1: block diagram of the vpx 3224d, vpx 3225d clock gen. dco adc sync processing text slicer (vpx 3225d only) chroma demodulator line store luma filter video decoder mux adc i2c jtag video processing video interface cvbs/y chroma sda scl href vref field a[7:0] oeq b[7:0] pixclk llc vact yy c b c r c b c r mux mux port port
preliminary data sheet vpx 3225d, vpx 3224d 8 micronas 2. functional description the following sections provide an overview of the differ- ent functional blocks within the vpx. most of them are controlled by the fast processor ( ? fp ? ) embedded in the decoder. for controlling, there are two classes of regis- ters: i 2 c registers (directly addressable via i 2 c bus) and fp-ram registers (ram memory of the fp; indirectly ad- dressable via i 2 c bus). for further information, see sec- tion 2.14.1. 2.1. analog front-end this block provides the analog interfaces to all video in- puts and mainly carries out analog-to-digital conversion for the following digital video processing. a block dia- gram is given in fig. 2 ? 1. clamping, agc, and clock dco are digitally controlled. the control loops are closed by the embedded proces- sor. 2.1.1. input selector up to four analog inputs can be connected. three inputs (vin1 ? 3) are for input of composite video or s-vhs luma signal. these inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. two in- puts, one dedicated (cin) and one shared (vin1), are for connection of s-vhs carrier-chrominance signal. the chrominance input is internally biased and has a fixed gain amplifier. 2.1.2. clamping the composite video input signals are ac coupled to the ic. the clamping voltage is stored on the coupling ca- pacitors and is generated by digitally controlled current sources. the clamping level is the back porch of the vid- eo signal. s-vhs chroma is ac coupled. the input pin is internally biased to the center of the adc input range. 2.1.3. automatic gain control a digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/ ? 4.5 db in 64 logarithmic steps to the optimal range of the adc. the gain of the video input stage including the adc is 213 steps/v with the agc set to 0 db. 2.1.4. analog-to-digital converters two adcs are provided to digitize the input signals. each converter runs with 20.25 mhz and has 8-bit reso- lution. an integrated bandgap circuit generates the re- quired reference voltages for the converters. the two adcs are of a 2-stage subranging type. 2.1.5. adc range the adc input range for the various input signals and the digital representation is given in table 2 ? 1 and fig. 2 ? 2. the corresponding output signal levels of the vpx 32xx are also shown. 2.1.6. digitally controlled clock oscillator the clock generation is also a part of the analog front end. the crystal oscillator is controlled digitally by the fp; the clock frequency can be adjusted within ? 1: analog front-end input mux cvbs/y cvbs/y cvbs/y/c chroma vin3 vin2 vin1 cin clamp bias reference generation gain frequency adc adc dcvo ? 4.5 db
vpx 3225d, vpx 3224d preliminary data sheet 9 micronas table 2 ? 1: adc input range for pal input signal and corresponding output signal ranges signal input level [mv pp ] adc range yc r c b output range ? 6 db 0 db + 4.5 db [steps] [steps] cvbs 100% cvbs 667 1333 2238 252 ? 75% cvbs 500 1000 1679 213 ? video (luma) 350 700 1175 149 224 sync height 150 300 504 64 ? clamp level 68 16 chroma burst 300 64 ? 100% chroma 890 190 128 112 75% chroma 670 143 128 84 bias level 128 128 255 192 128 0 black white 217 video = 100 ire sync = 41 ire 68 32 192 128 228 80 32 upper headroom = 38 steps = 1.4 db = 25 ire lower headroom = 4 steps = 0.2 db headroom = 56 steps = 2.1 db = clamp level cvbs/y chroma 75% chroma 100% chroma burst fig. 2 ? 2: adc ranges for cvbs/luma and chroma, pal input signal
preliminary data sheet vpx 3225d, vpx 3224d 10 micronas 2.2. color decoder in this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. the color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. a block diagram of the color decoder is shown in fig. 2 ? 4. the luma, as well as the chroma processing, is shown here. the color decoder also provides several special modes; for example, wide band chroma format which is intended for s-vhs wide bandwidth chroma. the output of the color decoder is yc r c b in a 4:2:2 for- mat. 2.2.1. if-compensation with off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color sub- carrier is compensated. four different settings of the if- compensation are possible: ? flat (no compensation) ? 6 db /octave ? 12 db /octave ? 10 db/mhz the last setting gives a very large boost to high frequen- cies. it is provided for secam signals that are decoded using a saw filter specified originally for the pal stan- dard. fig. 2 ? 3: freq. response of chroma if-compensation db mhz 10 3.5 3.75 4 4.25 4.5 5 0 ? 10 ? 15 ? 20 ? 5 5 4.75 2.2.2. demodulator the entire signal (which might still contain luma) is now quadrature-mixed to the baseband. the mixing frequen- cy is equal to the subcarrier for pal and ntsc, thus achieving the chroma demodulation. for secam, the mixing frequency is 4.286 mhz giving the quadrature baseband components of the fm modulated chroma. after the mixer, a lowpass filter selects the chroma com- ponents; a downsampling stage converts the color dif- ference signals to a multiplexed half rate data stream. the subcarrier frequency in the demodulator is gener- ated by direct digital synthesis; therefore, substandards such as pal 3.58 or ntsc 4.43 can also be demodu- lated. chroma if compensation dc-reject mixer lowpass filter phase/freq. acc color-pll / color-acc 1 h delay mux mux cross- notch filter demodulator luma / cvbs luma chroma fig. 2 ? 4: color decoder switch
vpx 3225d, vpx 3224d preliminary data sheet 11 micronas 2.2.3. chrominance filter the demodulation is followed by a lowpass filter for the color difference signals for pal/ntsc. secam requires a modified lowpass function with bell-filter characteristic. at the output of the lowpass filter, all luma information is eliminated. the lowpass filters are calculated in time multiplex for the two color signals. four bandwidth settings (narrow, normal, broad, wide) are available for each standard. the filter passband can be shaped with an extra peaking term at 1.25 mhz. for pal/ntsc, a wide band chroma filter can be selected. this filter is intended for high bandwidth chroma signals; for example, a nonstandard wide bandwidth s-vhs signal. fig. 2 ? 5: frequency response of chroma filters pal/ntsc secam db mhz 0 012345 ? 10 ? 20 ? 30 ? 40 ? 50 db mhz 0 012345 ? 10 ? 20 ? 30 ? 40 ? 50 2.2.4. frequency demodulator the frequency demodulator for demodulating the se- cam signal is implemented as a cordic-structure. it calculates the phase and magnitude of the quadrature components by coordinate rotation. the phase output of the cordic processor is differen- tiated to obtain the demodulated frequency. after a pro- grammable deemphasis filter, the dr and db signals are scaled to standard c r c b amplitudes and fed to the cross- over-switch. 2.2.5. burst detection in the pal/ntsc-system, the burst is the reference for the color signal. the phase and magnitude outputs of the cordic are gated with the color key and used for controlling the phase-lock-loop (apc) of the demodula- tor and the automatic color control (acc) in pal/ntsc. the acc has a control range of +30 ... ? 6 db. for secam decoding, the frequency of the burst is mea- sured. thus, the current chroma carrier frequency can be identified and is used to control the secam proces- sing. the burst measurements also control the color kill- er operation; they can be used for automatic standard detection as well. 2.2.6. color killer operation the color killer uses the burst-phase / burst-frequency measurement to identify a pal/ntsc or secam color signal. for pal/ntsc, the color is switched off (killed) as long as the color subcarrier pll is not locked. for se- cam, the killer is controlled by the toggle of the burst fre- quency. the burst amplitude measurement is used to switch off the color if the burst amplitude is below a pro- grammable threshold. thus, color will be killed for very noisy signals. the color amplitude killer has a program- mable hysteresis. 2.2.7. pal compensation / 1-h comb filter the color decoder uses one fully integrated delay line. only active video is stored. the delay line application depends on the color stan- dard: ? ntsc: 1-h comb filter or color compensation ? pal: color compensation ? secam: crossover-switch
preliminary data sheet vpx 3225d, vpx 3224d 12 micronas in the ntsc compensated mode, fig. 2 ? 7 c), the color signal is averaged for two adjacent lines. thus, cross- color distortion and chroma noise is reduced. in the ntsc combfilter mode, fig. 2 ? 7 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. the loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. 2.2.8. luminance notch filter if a composite video signal is applied, the color informa- tion is suppressed by a programmable notch filter. the position of the filter center frequency depends on the subcarrier frequency for pal/ntsc. for secam, the notch is directly controlled by the chroma carrier fre- quency. this considerably reduces the cross-lumi- nance. the frequency responses for all three systems are shown in fig. 2 ? 6. in s-vhs mode, this filter is by- passed. db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 db mhz 10 02 4 68 10 0 ? 10 ? 20 ? 30 ? 40 pal/ntsc notch filter fig. 2 ? 6: frequency responses of the luma notch filter for pal, ntsc, secam secam notch filter chroma notch filter 8 chroma process. cvbs y 1 h delay 8 cvbs chroma process. notch filter y 8 chroma process. luma y 8 a) conventional b) s-vhs d) comb filter fig. 2 ? 7: ntsc color decoding options c c r b notch filter 1 h delay 8 chroma process. cvbs y c) compensated c r c b c r c b c r c b chroma notch filter 1 h delay 8 chroma process. cvbs y 8 chroma process. luma y 8 1 h delay a) conventional b) s-vhs fig. 2 ? 8: pal color decoding options c r c b c r c b mux notch filter 1 h delay 8 chroma process. cvbs y fig. 2 ? 9: secam color decoding c r c b
vpx 3225d, vpx 3224d preliminary data sheet 13 micronas 2.3. video sync processing fig. 2 ? 10 shows a block diagram of the front-end sync processing. to extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 mhz. the sync is sep- arated by a slicer; the sync phase is measured. the in- ternal controller can select variable windows to improve the noise immunity of the slicer. the phase comparator measures the falling edge of sync, as well as the inte- grated sync pulse. the sync phase error is filtered by a phase-locked loop that is computed by the fp. all timing in the front-end is derived from a counter that is part of this pll, and it thus counts synchronously to the video signal. a separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. this information is processed by the fp and used for gain control and clamping. for vertical sync separation, the sliced video signal is in- tegrated. the fp uses the integrator value to derive ver- tical sync and field information. frequency and phase characteristics of the analog vid- eo signal are derived from pll1. the results are fed to the rest of the video processing system in the backend. the resizer unit uses them for data interpolation and orthogonalization. a separate timing block derives the timing reference signals href and vref from the hori- zontal sync. 2.4. macrovision detection (version d4 only) video signals from macrovision encoded vcr tapes are decoded without loss of picture quality. however, it might be necessary in some applications to detect the pres- ence of macrovision encoded video signals. this is pos- sible by reading a set of i 2 c registers (fp-ram 0x170 ? 0x179) in the video front-end. macrovision encoded video signals typically have agc pulses and pseudo sync pulses added during vbi. the amplitude of the agc pulses is modulated in time. the macrovision detection logic measures the vbi lines and compares the signal against programmable thresholds. the window in which the video lines are checked for ma- crovision pulses can be defined in terms of start and stop line (e.g. 6 ? 15 for ntsc). fig. 2 ? 10: sync separation block diagram lowpass 1 mhz & sync slicer horizontal sync separation clamp & signal measurement phase comparator & lowpass counter front-end timing front sync generator clock synthesizer syncs front sync skew vblank field clock h/v syncs clamping video input color key fifo_write pll1
preliminary data sheet vpx 3225d, vpx 3224d 14 micronas 2.5. component processing recovery of the ycbcr components by the decoder is followed by horizontal resizing and skew compensation. contrast enhancement with noise shaping can also be applied to the luminance signal. vertical resizing is sup- ported via line dropping. fig. 2 ? 11 illustrates the signal flow through the compo- nent processing stage. the ycbcr 4:2:2 samples are separated into a luminance path and a chrominance path. the luma filtering block applies anti-aliasing low- pass filters with cutoff frequencies adapted to the num- ber of samples after scaling, as well as peaking and cor- ing. the resize and skew blocks alter the effective sampling rate and compensate for horizontal line skew. the ycbcr samples are buffered in a fifo for continu- ous burst at a fixed clock rate. for luminance samples, the contrast and brightness can be adjusted and noise shaping applied. in the chrominance path, cb and cr samples can be swapped. without swapping, the first valid video sample is a cb sample. chrominance gain can be adjusted in the color decoder. resize skew resize skew sequence control f i f o 16 bit contrast, brightness & noise shaping active video reference latch luma filter with peaking & coring y out cr out y in cbcr in luma phase shift chroma phase shift fig. 2 ? 11: component processing stage cb/cr- swapping table 2 ? 2: several rasters supported by the resizer ntsc pal/secam format name 640 x 480 768 x 576 square pixels for broadcast tv (4:3) 704 x 480 704 x 576 input raster for mpeg-2 320 x 240 384 x 288 square pixels for tv (quarter resolution) 352 x 240 352 x 288 cif ? input raster for mpeg-1, h.261 160 x 120 192 x 144 square pixels for tv (1/16 resolution), h.324, h.323 176 x 120 176 x 144 qcif ? input raster for h.261 32 x 24 32 x 24 video icons for graphical interfaces (square)
vpx 3225d, vpx 3224d preliminary data sheet 15 micronas 2.5.1. horizontal resizer the operating range of the horizontal resizer was cho- sen to serve the widest possible range of applications and source formats (number of lines, aspect ratio, etc...). table 2 ? 2 lists several examples for video sourced from 525/625 line tv systems. the horizontal resizer alters the sampling raster of the video signal, thereby varying the number of pixels (npix) in the active portion of the video line. the number of pix- els per line is selectable within a range from 32 to 864 in increments of 2 pixels (see section 2.10.: windowing the video field). table 2 ? 2 gives an overview of several supported video rasters. the visual quality of a sampling rate conversion operation depends on two factors: ? the frequency response of the individual filters, and ? the number of available filters from which to choose. the vpx is equipped with a battery of fir filters to cover the five octave operating range of the resizer. fig. 2 ? 12 shows the magnitude response of five example filters corresponding to 1054, 526, 262, 130, and 32 pixels. the density of the filter array can be seen in fig. 2 ? 13. the magnitude response of 50 filters lying next to each other are shown. nevertheless, these are only 10% of all filters shown. as a whole, the vpx comes with a battery of 512 fir filters. showing these 512 filters in fig. 2 ? 12 would result in a large black area. this dense array of fil- ters is necessary in order to maintain constant visual quality over the range of allowable picture sizes. the al- ternative would be to use a small number of filters whose cutoff frequencies are regularly spaced over the spec- trum. however, it has been found that using few filters leads to visually annoying threshold behavior. these ef- fects occur when the filters are changed in response to variations in the picture size. filter selection is performed automatically by the internal processor based on the selected resizing factor (npix). this automated selection is optimized for best visual performance. db fig. 2 ? 12: freq. response of 5 widely spaced filters 0 ? 10 ? 20 ? 30 ? 40 mhz 010203040 fig. 2 ? 13: freq. response of 50 neighbored filters 0 ? 4 ? 6 ? 8 ? 10 mhz 0 0.5 1.5 2 3 ? 2 ? 12 1 2.5 db
preliminary data sheet vpx 3225d, vpx 3224d 16 micronas 2.5.2. skew correction the vpx delivers orthogonal pixels with a fixed clock even in the case of non-broadcast signals with substan- tial horizontal jitter (vcrs, laser disks, certain portions of the 6 o ? clock news...). this is achieved by highly accurate sync slicing com- bined with post correction. immediately after the analog input is sampled, a horizontal sync slicer tracks the posi- tion of sync. this slicer evaluates, to within 1.6 ns, the skew between the sync edge and the edge of the pixel- clock. this value is passed as a skew on to the phase shift filter in the resizer. the skew is then treated as a fixed initial offset during the resizing operation. the skew block in the resizer performs programmable phase shifting with subpixel accuracy. in the luminance path, a linear interpolation filter provides a phase shift between 0 and 31/32 in steps of 1/32. this corresponds to an accuracy of 1.6 ns. the chrominance signal can be shifted between 0 and 7/8 in steps of 1/8. 2.5.3. peaking and coring the horizontal resizer comes with an extra peaking filter for sharpness control. the center frequency of the peak- ing filter is automatically adjusted to the image size in 512 steps. the peaking value to each center frequency can be controlled by the user with up to eight steps via fp-ram 0x126/130. fig. 2 ? 14 shows the magnitude re- sponse of the eight steps of the peaking filter corre- sponding to an image size of 320 pixels. after the peaking filter, an additional coring filter is imple- mented to the horizontal resizer. the coring filter sub- tracts 0, 1/2, 1, or 2 lsbs of the higher frequency part of the signal. note, that coring can be performed indepen- dently of the peaking value adjustment. fig. 2 ? 14: frequency response of peaking filter 10 ? 10 ? 20 ? 30 mhz 01 34 6 0 25 db 2.5.4. ycbcr color space the color decoder outputs luminance and one multi- plexed chrominance signal at a sample clock of 20.25 mhz. active video samples are flagged by a sepa- rate reference signal. internally, the number of active samples is 1080 for all standards (525 lines and 625 lines). the representation of the chroma signals is the itu-r 601 digital studio standard. in the color decoder, the weighting for both color differ- ence signals is adjusted individually. the default format has the following specification: ? y = 224*y + 16 (pure binary), ? c r = 224*(0.713*(r ? y)) + 128 (offset binary), ? c b = 224*(0.564*(b ? y)) + 128 (offset binary). 2.5.5. video adjustments the vpx provides a selectable gain (contrast) and offset (brightness) for the luminance samples, as well as addi- tional noise shaping. both the contrast and brightness factors can be set externally via i 2 c serial control of fp- ram 0x127,128,131, and 132. fig. 2 ? 15 gives a func- tional description of this circuit. first, a gain is applied, yielding a 10-bit luminance value. the conversion back to 8-bit is done using one of four selectable techniques: simple rounding, truncation,1-bit error diffusion, or 2-bit error diffusion. bit[8] in the ? contrast ? -register selects be- tween the clamping levels 16 and 32. i out = c * i in + b c = 0...63/32 in 64 steps b = ?127...128 in 256 steps in the chrominance path, cb and cr samples can be swapped with bit[8] in fp-ram 0x126 or 130. adjust- ment of color saturation and gain is provided via fp- ram 0x30 ? 33 (see section 2.2.5.). fig. 2 ? 15: contrast and brightness adjustment rounding truncation 1 bit err. diff. 2 bit err. diff. contrast select brightness fp-ram registers
vpx 3225d, vpx 3224d preliminary data sheet 17 micronas 2.6. video output interface contrary to the component processing stage running at a clock rate of 20.25 mhz, the output formatting stage (fig. 2 ? 16) receives the video samples at a pixel trans- port rate of 13.5 mhz. it supports 8 or 16-bit video for- mats with separate or embedded reference signals, pro- vides bus shuffling, and channels the output via one or both 8-bit ports. data transfer is synchronous to the in- ternally generated 13.5 mhz pixel clock. the format of the output data depends on three parame- ters: ? the selected output format yuv 4:2:2, separate syncs yuv 4:2:2, itu-r656 yuv 4:2:2, embedded reference codes (bstream) ? the number of active ports (a only, or both a and b) ? clock speed (single, double, half). in 8-bit modes using only port a for video data, port b can be used as programmable output. 2.6.1. output formats the vpx supports the yuv 4:2:2 video format only. dur- ing normal operation, all reference signals are output separately. to provide a reduced video interface, the vpx offers two possibilities for encoding timing refer- ences into the video data stream: an itu-r656 com- pliant output format with embedded timing reference headers and a second format with single timing control codes in the video stream. the active output format can be selected via fp-ram 0x150 [format]. 2.6.1.1. yuv 4:2:2 with separate syncs/itu-r601 the default output format of the vpx is a synchronous 16-bit yuv 4:2:2 data stream with separate reference signals. port a is used for luminance and port b for chro- minance-information. video data is compliant to itu- r601. bit[1:0] of fp-ram 0x150 has to be set to 00. fig- ure 2 ? 17 shows the timing of the data ports and the reference signals in this mode. fig. 2 ? 16: output format stage output formats bus shuffler output multiplex clock generation 16 8 8 8 8 8 8 reference signals video samples port a port b pixclk llc llc2 href vref vact oe fig. 2 ? 17: detailed data output (single clock mode) chrominance (port b) vact llc c 1 c n ? 1 c n luminance (port a) y 1 y n ? 1 y n pixclk
preliminary data sheet vpx 3225d, vpx 3224d 18 micronas 2.6.1.2. embedded reference headers/itu-r656 the vpx supports an output format which is designed to be compliant with the itu-r656 recommendation. it is activated by setting bit[1:0] of fp-ram 0x150 to 01. the 16-bit video data must be multiplexed to 8 bit at the double clock frequency (27 mhz) via fp-ram 0x154, bit 9 set to 1 (see also section 2.6.3.: output multiplexer). in this mode, video samples are in the following order: cb, y, cr, y, ... the data words 0 and 255 are protected since they are used for identification of reference head- ers. this is assured by limitation of the video data. tim- ing reference codes are inserted into the data stream at the beginning and the end of each video line in the fol- lowing way: a ? start of active video ? -header (sav) is in- serted before the first active video sample. the ? end of active video ? -code (eav) is inserted after the last active video sample. they both contain information about the field type and field blanking. the data words occurring during the horizontal blanking interval between eav and sav are filled with 0x10 for luminance and 0x80 for chro- minance information. table 2 ? 3 shows the format of the sav and eav header. note that the following changes and extensions to the itu-r656 standard have been included to support hori- zontal and vertical scaling, transmission of vbi-data, etc.: ? both the length and the number of active video lines varies with the selected window parameters. for com- pliance with the itu-r656 recommendation, a size of 720 samples per line must be selected for each win- dow. to enable a constant line length even in the case of different scaling values for the video windows, the vpx provides a programmable ? active video ? signal (see section 2.8.4.). ? during blanked lines, the vact signal is suppressed. vbi-lines can be marked as blanked or active, thus al- lowing the choice of enabled or suppressed vact dur- ing the vbi-window. the vertical field blanking flag (v) in the sav/eav header is set to zero in any line with enabled vact signal (valid vbi or video lines). ? during blanked lines, sav/eav headers can be sup- pressed in pairs with fp-ram 0x150, bit9. to assure vertical sync detection, some sav/eav headers are inserted during field blanking. ? the flags f, v, and h encoded in the sav/eav headers change on sav. with fp-ram 0x150, bit10 set to 1, they change on eav. the programmed windows, how- ever, are delayed by one line. header suppression is applied for eav/sav pairs. ? for data within the vbi-window (e.g. sliced or raw tele- text data), the user can select between limitation or re- duction to 7-bit resolution with an additional lsb as- suring odd parity (0 and 255 never occur). this option can be selected via fp-ram 0x150 [range]. ? ancillary data blocks may be longer than 255 bytes (for raw data) and are transmitted without checksum. the secondary data id is used as high byte of the data count (dc1; see table 2 ? 5). ? ancillary data packets must not follow immediately af- ter eav or sav. ? the total number of clock cycles per line, as well as valid cycles between eav and sav may vary. table 2 ? 3: coding of the sav/eav-header bit no. word msb lsb 7 6 5 4 3 2 1 0 first 1 1 1 1 1 1 1 1 second 0 0 0 0 0 0 0 0 third 0 0 0 0 0 0 0 0 fourth 1 f v h p3 p2 p1 p0 f = 0 during field 1, f = 1 during field 2 v = 0 during active lines v = 1 during vertical field blanking h = 0 in sav, h = 1 in eav the bits p0, p1, p2, and p3 are protection bits. their states are dependent on the states of f, v, and h as shown in table 2 ? 4. table 2 ? 4: coding of the protection bits bit no. code (hex) msb lsb f v h p3 p2 p1 p0 80 1 0 0 0 0 0 0 0 9d 1 0 0 1 1 1 0 1 ab 1 0 1 0 1 0 1 1 b6 1 0 1 1 0 1 1 0 c7 1 1 0 0 0 1 1 1 da 1 1 0 1 1 0 1 0 ec 1 1 1 0 1 1 0 0 f1 1 1 1 1 0 0 0 1 the vpx also supports the transmission of vbi-data as vertical ancillary data during blanked lines in the interval starting with the end of the sav and terminating with the beginning of eav. in this case, an additional header is in- serted directly before the valid active data. in this mode, the position of sav and eav depends on the settings for the programmable vact signal. these parameters will
vpx 3225d, vpx 3224d preliminary data sheet 19 micronas be checked and corrected if necessary to assure an ap- propriate size of vact for both data and ancillary header. table 2 ? 5 shows the coding of the ancillary header in- formation. the word i[2:0] contains a value for data type identification (1 for sliced and 3 for raw data during odd fields, 5 for sliced and 7 for raw data during even fields). m[5:0] contains the msbs and l[5:0] the lsbs of the number of following d-words (32 for sliced data, 285 for raw data). dc1 is normally used as secondary data id. the value 0 for m[5:0] in the case of sliced data marks an undefined format. bit 6 is even parity for bit5 to bit0. bit 7 is the inverted parity flag. note that the following user data words (video data) are either limited or have odd parity to assure that 0 and 255 will not occur. bit 3 in ram 0x150 selects between these two options. table 2 ? 5: coding of the ancillary header information bit no. word msb lsb 7 6 5 4 3 2 1 0 pream1 0 0 0 0 0 0 0 0 pream2 1 1 1 1 1 1 1 1 pream3 1 1 1 1 1 1 1 1 did np p 0 1 0 i2 i1 i0 dc1 np p m5 m4 m3 m2 m1 m0 dc2 np p l5 l4 l3 l2 l1 l0 constant during horizontal blanking y = 10 hex ; c r = c b = 80 hex c b y c r y ... sav eav sav eav sav: ? start of active video ? header eav: ? end of active video ? header c b y c r y ... fig. 2 ? 18: output of video or vbi data with embedded reference headers (according to itu-r656) vact digital video output dependent on window size current line length fig. 2 ? 19: detailed data output (double clock mode) c rn ? 1 y n c r1 y 2 c bn ? 1 y n ? 1 c b1 y 1 sav 1 sav 2 sav 3 sav 4 10h 80h 80h 10h eav 1 eav 2 eav 3 eav 4 data (port a) vact llc pixclk fig. 2 ? 20: output of vbi-data as ancillary data dependent on vbi-window size constant during horizontal blanking y = 10 hex ; c r = c b = 80 hex d 1 d 2 d 3 d 4 ... sav eav sav eav sav: ? start of active video ? header eav: ? end of active video ? header c b y c r y ... vact digital video output current line length anc size of programmable vact
preliminary data sheet vpx 3225d, vpx 3224d 20 micronas 2.6.1.3. embedded timing codes (bstream) in this mode, several event words are inserted into the pixel stream for timing information. it is activated by set- ting bit[1:0] of fp-ram 0x150 to 10. each event word consists of a chrominance code value containing the phase of the color-multiplex followed by a luminance code value signalling a specific event. the allowed con- trol codes are listed in table 2 ? 6 and 2 ? 7. at the beginning and the end of each active video line, timing reference codes (start of active video: sav; end of active video: eav) are inserted with the beginning and the end of vact. since vact is suppressed during blanked lines, video data and sav/eav codes are pres- ent during active lines only. if raw/sliced data should be output, vact has to be enabled during the vbi window with bit 2 of fp-ram 0x138! in the case of several win- dows per field, the length of the active data stream per line can vary. since the qualifiers for active video (sav/ eav) are independent of the other reference codes, there is no influence on horizontal or vertical syncs, and sync generation can be performed even with several dif- ferent windows. for full compliance with applications re- quiring data streams of a constant size, the vpx pro- vides a mode with programmable ? video active ? signal vact which can be selected via bit 2 of fp-ram 0x140. the start and end positions of vact relative to href is determined by fp-ram 0x151 and 0x152. the delay of valid data relative to the leading edge of href is calcu- lated with the formulas given in table 2 ? 8 and 2 ? 9. the result can be read in fp-ram 0x10f (for window 1) and 0x11f (for window 2). be aware that the largest window defines the size of the needed memory. in the case of 1140 raw vbi-samples and only 32 scaled video sam- ples, the graphics controller needs 570 words for each line (the vbi-samples are multiplexed to luminance and chrominance paths). the leading edge of href indicates the beginning of a new video line. depending on the type of the current line (active or blanked), the corresponding horizontal refer- ence code is inserted. for big window sizes, the leading edge of href can arrive before the end of the active data. in this case, hardware assures that the control code for href is delayed and inserted after eav only. the vref control code is inserted at the falling edge of vref. the state of href at this moment indicates the current field type (href = 0: odd field; href = 1: even field). in this mode, the words 0,1,254, and 255 are reserved for data identifications. this is assured by limitation of the video data. table 2 ? 6: chrominance control codes chroma value phase information fe cr pixel ff cb pixel 2.6.2. bus shuffler in the yuv 4:2:2 mode, the output of luminance data is on port a and chrominance data on port b. with the bus shuffler, luminance can be switched to port b and chro- minance to port a. in 8-bit double clock mode, shuffling can be used to swap the y and c components. it is se- lected with fp-ram 0x150. 2.6.3. output multiplexer during normal operation, a 16-bit yuv 4:2:2 data stream is transferred synchronous to an internally generated pixclk at a rate of 13.5 mhz. data can be latched onto the falling edge of pixclk or onto the rising edge of llc during high pixclk. in the double clock mode, lumi- nance and chrominance data are multiplexed to 8 bit and transferred at the double clock frequency of 27 mhz in the order cb, y, cr, y...; the first valid chrominance value being a cb sample. with shuffling switched on, y and c components are swapped. data can be latched with the rising edge of llc or alternating edges of pixclk. this mode is selected with bit 9 of fp-ram 0x154. all 8-bit modes use port a only. in this case, port b can be acti- vated as programmable output with bit 8 of fp-ram 0x154. bit 0 ? 7 determine the state of port b. 7:0 8 video data =0 =1 b[7:0] video port fp-ram 0x154 [outmux] fig. 2 ? 21: programmable output port 8 8 8 2.6.4. output ports the two 8-bit ports produce ttl level signals coded in binary offset. the ports can be tristated either via the output enable pin (oe ) or via i 2 c register 0xf2. for more information, see section 2.17. ? enable/disable of output signals ? .
vpx 3225d, vpx 3224d preliminary data sheet 21 micronas table 2 ? 7: luminance control codes luma value video event video event phase information 01 vact end last pixel was the last active pixel refers to the last pixel 02 vact begin next pixel is the first active pixel refers to the next pixel 03 href active line begin of an active video line refers to the current pixel 04 href blank line begin of a blank line refers to the current pixel 05 vref even begin of an even field refers to the current pixel 06 vref odd begin of an odd field refers to the current pixel fig. 2 ? 22: detailed data output with timing event codes (double clock mode) c rn ? 1 y n c r1 y 2 c bn ? 1 y n ? 1 c b1 y 1 ffh 02h 03h ffh feh 01h data (port a) vact llc pixclk href 2.7. video data transfer the vpx supports a synchronous video interface. video data arrives to each line at the output in an uninterrupted burst with a fixed transport rate of 13.5 mhz. the dura- tion of the burst is measured in clock periods of the trans- port clock and is equal to the number of pixels per output line. the data transfer is controlled via the signals: pixclk, vact, and llc. an additional clock signal llc2 can be switched to the tdo output pin to support different tim- ings. the vact signal flags the presence of valid output data. fig. 2 ? 23, 2 ? 24, and 2 ? 25 illustrate the relationship be- tween the video port data, vact, pixclk, and llc. whenever a line of video data should be suppressed (line dropping, switching between analog inputs), it is done by suppression of vact. 2.7.1. single and double clock mode data is transferred synchronous to the internally gener- ated pixclk. the frequency of pixclk is 13.5 mhz. the llc signal is provided as an additional support for both the 13.5 mhz and the 27 mhz double clock mode. the llc consists of a doubled pixclk signal (27 mhz) for interface to external components which rely on the philips transfer protocols. in the single clock mode, data can be latched onto the falling edge of pixclk or at the rising edge of llc during high pixclk. in double clock mode, output data can be latched onto both clock edges of pixclk or onto every rising edge of llc. combined with the half-clock mode, the available transfer band- widths at the ports are therefore 6.75 mhz, 13.5 mhz, and 27.0 mhz.
preliminary data sheet vpx 3225d, vpx 3224d 22 micronas 2.7.2. half clock mode for applications demanding a low bandwidth for the transmission between video decoder and graphics con- troller, the clock signal qualifying the output pixels (pixclk) can be divided by 2. this mode is enabled by setting bit 5 of the fp-ram 0x150 [halfclk]. note that the output format itu-r601 must be selected. the timing of the data and clock signals in this case is described in fig- ure 2 ? 25. if the half-clock mode is enabled, each second pulse of pixclk is gated. pixclk can be used as a qualifier for valid data. to ensure that the video data stream can be spread, the selected number of valid output samples should not exceed 400. chrominance (port b) vact llc c 1 c n ? 1 c n luminance (port a) y 1 y n ? 1 y n pixclk fig. 2 ? 23: output timing in single clock mode video (port a) vact llc c 1 c n ? 1 c n pixclk y 1 y n ? 1 y n fig. 2 ? 24: output timing in double clock mode chrominance (port b) vact llc luminance (port a) y 1 y n pixclk c 1 c n fig. 2 ? 25: output timing in half clock mode
vpx 3225d, vpx 3224d preliminary data sheet 23 micronas 2.8. video reference signals the complete video interface of the vpx runs at a clock rate of 13.5 mhz. it mainly generates two reference sig- nals for the video timing: a horizontal reference (href) and a vertical reference (vref). these two signals are generated by programmable hardware and can be ei- ther free running or synchronous to the analog input vid- eo. the video line standard (625/50 or 525/60) depends on the tv-standard selected with fp-ram 0x20 [sdt]. the polarity of both signals is individually selectable via fp-ram 0x153. the circuitry which produces the vref and href sig- nals has been designed to provide a stable, robust set of timing signals, even in the case of erratic behavior at the analog video input. depending on the selected oper- ating mode given in fp-ram 0x140 [settm], the period of the href and vref signals are guaranteed to re- main within a fixed range. these video reference signals can therefore be used to synchronize the external com- ponents of a video subsystem (for example the ics of a pc add-in card). in addition to the timing references, valid video samples are marked with the ? video active ? qualifier (vact). in or- der to reduce the signal number of the video interface, several 8-bit modes have been implemented, where the reference signals are multiplexed into the data stream (see section 2.6.1.). 2.8.1. href fig. 2 ? 26 illustrates the timing of the href signal rela- tive to the analog input. the inactive period of href has a fixed length of 64 periods of the 13.5 mhz output clock rate. the total period of the href signal is expressed as nominal and depends on the video line standard. analog video input href vpx delay fig. 2 ? 26: href relative to input video 4.7 nominal 2.8.2. vref figs. 2 ? 27 and 2 ? 28 illustrate the timing of the vref signal relative to field boundaries of the two tv stan- dards. the start of the vref pulse is fixed, while the length is programmable in the range between 2 and 9 video lines via fp-ram 0x153 [vlen]. 2.8.3. odd/even information (field) information on whether the current field is odd or even is supplied through the relationship between the edge (either leading or trailing) of vref and level of href. this relationship is fixed and shown in figs. 2 ? 27 and 2 ? 28. the same information can be supplied to the field pin, which can be enabled/disabled as output in fp-ram 0x153 [enfieldq]. fp-ram 0x153 [oepol] pro- grams the polarity of this signal. during normal operation the field flag is filtered since most applications need interlaced signals. after filtering, the field type is synchronized to the input signal only if the last 8 fields have been alternating; otherwise, it al- ways toggles. this filtering can be disabled with fp- ram 0x140 [disoef]. in this case, the field information follows the odd/even property of the input video signal.
preliminary data sheet vpx 3225d, vpx 3224d 24 micronas 1234567 input cvbs (50 hz), pal href vref 34567 8 910 625 input cvbs (60 hz), ntsc 361 t clk13.5 fig. 2 ? 27: vref timing for odd fields 361 t clk13.5 > 1 t clk13.5 field 2 .. 9 h 313 314 315 316 317 318 319 312 320 input cvbs (50 hz), pal 265 266 267 268 269 270 271 272 273 input cvbs (60 hz), ntsc 46 t clk13.5 href vref fig. 2 ? 28: vref timing for even fields 46 t clk13.5 > 1 t clk13.5 field 2 .. 9 h
vpx 3225d, vpx 3224d preliminary data sheet 25 micronas 2.8.4. vact the ? video active ? signal is a qualifier for valid video sam- ples. since scaled video data is stored internally, there are no invalid pixel within the vact interval. vact has a defined position relative to href depending on the window settings (see section 2.10.). the maximal win- dow length depends on the minimal line length of the in- put signal. it is recommended to choose window sizes of less than 800 pixels. sizes up to 864 are possible, but for non-standard input lines, vact is forced inactive 4 pixclk cycles before the next trailing edge of href. during the vbi-window, vact can be enabled or sup- pressed with fp-ram 0x138. within this window, the vpx can deliver either sliced text data with a constant length of 64 samples or 1140 raw input samples. for ap- plications that request a uniform window size over the whole field, a mode with a free programmable vact is supported [fp-ram 0x140, vactmode]. the start and end position for the vact signal relative to the trailing edge of href can be programmed within a range of 0 to 864 [fp-ram 0x151, 0x152]. in this case, vact no longer marks valid samples only. the position of the valid data depends on the window definitions. it is calculated from the internal processor. the calculated delay of vact relative to the trailing edge of href can be read via fp-ram 0x10f (window 1) or 0x11f (window 2). tables 2 ? 8 and 2 ? 9 show the formulas for the position of valid data samples relative to the trail- ing edge of href. fig. 2 ? 29 illustrates the temporal relationship between the vact and the href signals as a function of the number of pixels per output line and the horizontal di- mensions of the window. the duration of the inactive pe- riod of the href is fixed to 64 clock cycles. table 2 ? 8: delay of valid output data relative to the trailing edge of href (single clock mode) mode data delay data end video data (hbeg+hlen)*(720/npix) ? hlen for npix < 720 hbeg*(720/npix) for npix ? 9: delay of valid output data relative to the trailing edge of href (half clock mode) mode data delay data end video data (hbeg+hlen)*(720/npix) ? 2*hlen for npix < 360 hbeg*(720/npix) for npix ? 1 d n data end data delay 64 cycles fig. 2 ? 29: relationship between href and vact signals (single clock mode)
preliminary data sheet vpx 3225d, vpx 3224d 26 micronas 2.9. operational modes the relationship between the video timing signals (href and vref) and the analog input video is deter- mined by the selected operational mode. three such modes are available: the open mode , the forced mode , and the scan mode . these modes are selected via i 2 c commands [fp-ram 0x140, settm, lattm]. 2.9.1. open mode in the open mode, both the href and the vref signal track the analog video input. in the case of a change in the line standard (i.e. switching between the video input ports), href and vref automatically synchronize to the new input. when no video is present, both href and vref float to the idling frequency of their respective plls. during changes in the video input (drop-out, switching between inputs), the performance of the href and vref signals is not guaranteed. 2.9.2. scan mode in the scan mode, the href and vref signals are al- ways generated by free running hardware. they are therefore completely decoupled from the analog input. the output video data is always suppressed. the purpose of the scan mode is to allow the external controller to freely switch between the analog inputs while searching for the presence of a video signal. in- formation regarding the video (standard, source, etc...) can be queried via i 2 c read. in the scan mode, the video line standard of the vref and href signals can be changed via i 2 c command. the transition always occurs at the first frame boundary after the i 2 c command is received. fig. 2 ? 30, below, demonstrates the behavior of the vref signal during the transition from the 525/60 system to the 625/50 sys- tem (the width of the vertical reference pulse is exagger- ated for illustration). vref f odd f odd f even f even f odd time 16.683 ms i 2 c command to switch video timing standard selected timing standard becomes active (525/60) (625/50) fig. 2 ? 30: transition between timing standards 20.0 ms 33.367 ms 40.0 ms
vpx 3225d, vpx 3224d preliminary data sheet 27 micronas table 2 ? 10: transition behavior as a function of operating mode transition behavior as a function of operating mode transition mode behavior power up/reset (no video) open vref, href: floats to steady state frequency of internal pll no video ? timing signals continue unchanged in free running mode ? vact signal is suppressed video ? timing signals continue unchanged in free running mode ? vact signal is suppressed video ? timing signals continue unchanged in free running mode ? vact signal is suppressed
preliminary data sheet vpx 3225d, vpx 3224d 28 micronas 2.10. windowing the video field for each input video field, two non-overlapping video windows can be defined. the dimensions of these win- dows are supplied via i 2 c commands. the presence of two windows allows separate processing parameters such as filter responses and the number of pixels per line to be selected. external control over the dimensions of the windows is performed by i 2 c writes to a window-load-table (win- loadtab). for each window, a corresponding winload- tab is defined in a table of registers in the fp-ram [win- dow1: 0x120 ? 128; window2: 0x12a ? 132]. data written to these tables does not become active until the cor- responding latch bit is set in the control register fp- ram 0x140. a 2-bit flag specifies the field polarity over which the window is active [vlinei1,2]. vertically, as can be seen in fig. 2 ? 31, each window is defined by a beginning line given in fp-ram 0x120/12a, a number of lines to be read-in (fp-ram 0x121/12b), and a number of lines to be output (fp-ram 0x122/12c). each of these values is specified in units of video lines. line 1 window 1 window 2 begin # lines in, # lines out begin # lines in, # lines out fig. 2 ? 31: vertical dimensions of windows the option, to separately specify the number of input lines and the number of output lines, enables vertical compression. in the vpx, vertical compression is per- formed via simple line dropping. a nearest neighbor al- gorithm selects the subset of the lines for output. the presence of a valid line is signalled by the ? video active ? qualifier (or the corresponding sav/eav code in em- bedded sync modes). the numbering of the lines in a field of interlace video is dependent on the line standard. figs. 2 ? 33 and 2 ? 34 il- lustrate the mapping of the window dimensions to the actual video lines. the indices on the left are the line numbers relative to the beginning of the frame. the in- dices on the right show the numbering used by the vpx. as seen here, the vertical boundaries of windows are de- fined relative to the field boundary. spatially, the lines from field #1 are displayed above identically numbered from field #2. for example: on an interlace monitor, line #23 from field #1 is displayed directly above line #23 from field #2. there are a few restrictions to the vertical definition of the windows. windows must not overlap vertically but can be adjacent. the first allowed line with- in a field is line #10 for 525/60 standards and line #7 for 625/50 standards. the number of output lines cannot be greater than the number of input lines (no vertical zoom- ing). the combined height of the two windows cannot exceed the number of lines in the input field. horizontally, the windows are defined by a starting point defined in fp-ram 0x123/12d and the length in fp- ram 0x124/12e. they are both given relative to the number of pixels (npix) in the active portion of the line (fig. 2 ? 32) selected in fp-ram 0x125/12f. the scaling factor is calculated internally from npix. window h begin h length n pix fig. 2 ? 32: horizontal dimensions of sampling window 64 sec 53.33 sec
vpx 3225d, vpx 3224d preliminary data sheet 29 micronas 4 5 6 7 18 19 20 21 263 262 261 267 268 269 270 281 282 283 284 524 525 field 1 field 2 264 265 266 4 5 6 7 18 19 20 21 263 262 261 264 265 266 1 2 3 4 5 6 7 18 19 20 21 263 262 261 264 265 260 523 260 260 fig. 2 ? 33: mapping for 525/60 line systems there are some restrictions in the horizontal window definition. the total number of active pixels (npix) must be an even number. the maximum value for npix should be 800. values up to 864 are possible, but for short input lines, video data is not guaranteed at the end of the line since vact will be interrupted at the beginning of the next line. hlength should also be an even number. ob- viously, the sum of hbegin and hlength may not be greater than npix. window boundaries are defined by writing the dimen- sions into the associated winloadtab and then setting the corresponding latch bit in the control word fp-ram 0x140 [latwin]. window definition data is latched at the beginning of the next video frame. once the winload- tab data has been latched, the latch bit in the control word is reset. by polling the infoword (fp-ram 0x141), the external controller can know when the window boundary data has been read. window definition data can be changed only once per frame. multiple window definitions within a single frame time are ignored and can lead to error. field 1 field 2 335 336 337 338 622 623 624 625 621 22 23 24 25 311 310 309 312 313 308 22 23 24 25 311 310 309 312 313 308 22 23 24 25 311 310 309 312 308 fig. 2 ? 34: mapping for 625/50 line systems 1 2 3 4 1 2 3 4 314 1 315 2 316 3 317 4 2.11. temporal decimation to cope with bandwidth restrictions in a system, the vpx supports temporal dropping of video frames via sup- pression of the vact signal. dropping will be applied for video windows only. there is no influence on the state of the vbi-window. this mode can be activated for each video window by setting the enable flag in the corre- sponding winloadtab (fp-ram 0x121/12b). the selection in fp-ram 0x157 determines how many frames will be output within an interval of 3000 frames. note that this selection is applied for both video win- dows, but decimation can be enabled for each window separately. the number of valid frames is updated only if the corresponding latch flag in fp-ram 0x140 [lattdec] is set. frame dropping with temporal decimation can be combined with the field disable flags (fp-ram 0x121/12b). within valid video frames, each field type can be disabled separately.
preliminary data sheet vpx 3225d, vpx 3224d 30 micronas 2.12. data slicer the data slicer is only available on vpx 3225d. soft- ware drivers accessing the slicer i 2 c registers should therefore check the vpx part number. 2.12.1. slicer features ? 8-bit digital fbas input ? 8-bit unbuffered ascii data output ? internal sync separation ? pal and ntsc operation ? vbi and full-field mode ? automatic slicer adaptation ? text reception down to 30% eyeheight ? soft error correction ? simultaneous decoding of 4 different text services ? ? ? ? ? programmable text parameters for main service ? ? ? ? ? ? operation controlled by i 2 c registers 2.12.2. data broadcast systems table 2 ? 11 gives an overview of the most popular data broadcast systems throughout the world. the data slicer of the vpx 3225d can be programmed to acquire the dif- ferent data systems via a set of i 2 c registers. the various data broadcast systems are specified by a limited set of parameters: ? line multiplex (vbi) ? bit rate ? modulation ? start timing ? clock run-in (cri) ? framing code (frc) ? number of data bytes table 2 ? 11: data broadcast systems text system tv standard tv lines bitrate modulation timing cri frc no. bytes wst pal 6 ? 22 6.937500mbit/s nrz 10.3 ? 5555 ? x ? 27 ? x 42 vps pal 16 2.500000mbit/s bi-phase 12.5 ? 5555 ? x ? 51 ? x 13 wss pal 23 0.833333mbit/s bi-phase 11.0 ? 3c78 ? x ? f8 ? x 11 caption pal 21 1.006993mbit/s nrz 10.5 ? aaa0 ? x ? c2 ? x 4 vitc pal 6 ? 22 1.812500mbit/s nrz 11.2 ? 22 6.203125mbit/s nrz 10.5 ? 5555 ? x ? e7 ? x 37 wst ntsc 10 ? 21 5.727272mbit/s nrz 9.6 ? 5555 ? x ? 27 ? x 34 nabts ntsc 10 ? 21 5.727272mbit/s nrz 10.5 ? 5555 ? x ? e7 ? x 33 caption ntsc 21 1.006993mbit/s nrz 10.5 ? aaa0 ? x ? c2 ? x 4 2xcaption ntsc 10 ? 21 1.006993mbit/s nrz 10.5 ? 2aa0 ? x ? b7 ? x 4 vitc ntsc 10 ? 21 1.812500mbit/s nrz 11.2 ? 10 ? b ? 3
vpx 3225d, vpx 3224d preliminary data sheet 31 micronas 2.12.3. slicer functions the data slicer is inserted between the video adc and the video output interface (see fig. 1 ? 1). it operates completely independent of the video front-end proces- sing and has its own sync separator and a separate set of i 2 c registers. figure 2 ? 35 shows a more detailed block diagram of the digital data slicer. sync filter bit slicer formatter dout dval 8 i 2 c register i 2 c bus din digital text slicer 8 fig. 2 ? 35: slicer block diagram 20.25 mhz 2.12.3.1. input the slicer receives an 8-bit digitized fbas signal which is clamped to the back porch level. the teletext signal amplitude can vary to a certain degree ( ? 13 shows with which i 2 c registers the text parameters are programmed and what the fixed settings for the side ser- vices are. 2.12.3.4. output the slicer delivers a synchronous burst of decoded teletext data bytes together with a data valid signal. this data stream is fed into the video fifo of the vpx back- end. the data rate depends on the teletext bit rate (divided by 8), the length of the burst is programmable. the burst can optionally be extended to 64 bytes inde- pendently of the selected teletext service (fill64 mode). the dummy bytes needed to fill the burst to 64 bytes are delivered at a rate of 20.25 mhz. normally, there is no output during lines without text transmission or unknown text signals. for some applications, it is necessary to have constant memory mapping. therefore, the slicer can be forced to output 64 bytes per line even if no text is detected (dump mode). the first 3 bytes of the data burst carry information to identify the received teletext service. the 2 byte line number contains a free running frame counter which can be used to identify data loss in the framebuffer of a cap- ture application. the field bit can be used to identify field dependent services such as caption. the 10-bit line number corresponds to the standard line counting scheme of a pal composite video signal; in case of ntsc, the value ? 3 ? is subtracted.
preliminary data sheet vpx 3225d, vpx 3224d 32 micronas the number of useful data bytes at the output is pro- grammable and should be set accordingly to the se- lected teletext standard. to get ? n ? data bytes, the value ? n+1 ? has to be programmed, because of the additional framing code byte. in case of dump mode, byte numbers ? 1 ? and ? 2 ? are also valid for lines without detected text data. they are then followed by 62 dummy bytes. table 2 ? 12: slicer output format byte number byte format bit format 1 line number high b[7:3] frame counter b[2] odd field b[1:0] line number[9:8] 2 line number low b[7:0] line number[7:0] 3 framing code b[7:0] as transmitted 4 1st data byte b[7:0] as transmitted . ... ... byte_cnt+2 last data byte b[7:0] as transmitted . dummy byte b[7:0] 00000000 . ... ... 64 dummy byte b[7:0] 00000000 table 2 ? 13: slicer programming (shaded values are hard wired) programmable parameter i2c register (hex) main service side services parameter (hex) e.g. wst vps wss caption text reception c9 on/off on/off on/off on/off tv standard c9 pal/ntsc pal pal ntsc tv lines c9 vbi/full field 16 23 21 bitrate c1, c2 702 506 506 102 reference bb, bc, bd 27 55 55 51 55 55 f8 3c 78 c2 aa a0 mask b8, b9, ba 00 00 03 00 00 00 00 00 00 00 00 1f tolerance ce 01 01 01 01 01 01 01 01 01 01 01 01 byte_cnt cf 43 28 14 5 64 byte mode cf on/off dump mode cf on/off adaption c7 on/off off soft error correction c7 on/off off
vpx 3225d, vpx 3224d preliminary data sheet 33 micronas 2.13. vbi data acquisition the vpx supports two different data acquisition modes for the vertical blanking interval: a bypass mode for raw data of the vertical blanking interval and a data slicer mode in which dedicated hardware provides constant packets of already decoded vbi-data. the data slicer mode is only available on vpx 3225d. for both services, the start and end line of a vertical blanking interval (vbi) window can be defined for each field with fp-ram 0x134 ? 137. teletext data can occur between lines 6 and 23 of each field. however, the vbi- window is freely programmable. it is possible to select the whole field (beginning with line #3). if video windows are enabled, the vbi-window should end two lines be- fore the first valid line of the next video window. the vbi- window can be activated via bit[0] in fp-ram 0x138. the identification of valid vbi-lines is possible with the vact-signal (or the ? active line ? -flags in the modes with embedded syncs) or a special ? data active ? signal on the tdo pin. bit[10] of fp-ram 0x154 selects between these two cases. in the default mode, vact is used. the output of both signals can be suppressed optionally with bit[2] of fp-ram 0x138. in this case, the graphic control- ler has to use only the href signal to mask the active video data. in the itu-r656 mode, vbi-data can be transmitted as vertical ancillary data (with 7 bit resolution + odd parity). the selections for the vbi-window will be updated by setting bit[11] in fp-ram 0x138. 2.13.1. raw vbi data the raw data mode is enabled with bit[1] of fp-ram 0x138 (vbimode). this mode bypasses the luminance processing of the video front-end and delivers unmodi- fied video samples from the adc to the output ports. during lines within the vbi-window, specified by the user settings in the corresponding load-table, the vpx internally acquires 1140 raw data bytes of the luminance input at a rate of 20.25 mhz corresponding to 56.296 ? 37). chrominance data is not valid. the raw data samples are multiplexed inter- nally to 570x16 bit on the luminance and chrominance port. the external timing corresponds to the video mode with 570 output samples for an uncropped window. figure 2 ? 36 shows the timing of both data ports and the necessary reference signals in this mode. fig. 2 ? 37: horizontal dimensions of the window for raw vbi-data 53.33 s active video 64 s 1140 samples (56.296 s) chrominance (port b) vact or tdo* llc d 1 d 1137 d 1139 luminance (port a) d 2 d 1138 d 1140 pixclk fig. 2 ? 36: timing during lines with raw vbi-data (single clock mode) * depending on bit[10] of fp-ram 0x154
preliminary data sheet vpx 3225d, vpx 3224d 34 micronas 2.13.2. sliced vbi data the sliced data mode is enabled with bit[1] of the fp-ram 0x138 (vbimode). this mode uses the inte- grated data slicer (available only on vpx 3225d) and delivers decoded data samples to the output ports. the data slicer provides data packets of a constant size (filled with dummy bytes). the data packets have a de- fault size of 64 bytes. to reduce the data rate for text sys- tems with a smaller number of data bytes, the packet size can be reduced via fp-ram 0x139. during lines within the vbi-window, specified by the user settings in the corresponding load-table, the vpx inter- nally multiplexes the data slicer packets onto the lumi- nance and chrominance outputs. since the values 0, 254, and 255 are protected in the 8-bit output modes (itu-r656, bstream), each slicer sample is separated into two nibbles for transmission. table 2 ? 14 shows the implemented data formats. in each path, one nibble is transmitted twice. the lsb is inverted for odd parity. this assures that the values 0 and 255 will not occur (for the detection of embedded syncs). in the mode with embedded timing event codes, chrominance data will be limited additionally. no signifi- cant information will be lost since only bit 0 and 1 will be modified. figure 2 ? 38 shows the timing of data and ref- erence signals in this mode. table 2 ? 14: splitting of sliced data to luminance and chrominance output bit no. word msb lsb 7 6 5 4 3 2 1 0 slicer data s7 s6 s5 s4 s3 s2 s1 s0 chroma output s7 s6 s5 s4 s7 s6 s5 s4 luma output s3 s2 s1 s0 s3 s2 s1 s0 the splitting described above can be disabled by setting bit 6 in the ? format_select ? register. in this case, the sliced samples will be transmitted in the luminance path only. to avoid modification of valid data, the limitation of lumi- nance data in the 8-bit output modes should be sup- pressed with bit 8 in the same register (note that lumi- nance codes will not be protected). chrominance (port b) vact llc d 1 (msbs) d 63 (msbs) d 64 (msbs) luminance (port a) d 1 (lsbs) d 63 (lsbs) d 64 (lsbs) pixclk fig. 2 ? 38: timing during lines with sliced vbi-data (single clock mode)
vpx 3225d, vpx 3224d preliminary data sheet 35 micronas 2.14. control interface 2.14.1. overview communication between the vpx and the external con- troller is performed serially via the i 2 c bus (pins scl and sda). there are basically two classes of registers in the vpx. the first class of registers are the directly addressable i 2 c registers. these are registers embedded directly in the hardware. data written to these registers is inter- preted combinatorially directly by the hardware. these registers are all a maximum of 8-bits wide. the second class of registers are the ? fp-ram regis- ters ? , the memory of the onboard microcontroller (micro- nas fast processor). data written into this class of regis- ters is read and interpreted by the fp ? s micro-code. internally, these registers are 12 bits wide. communica- tions with these registers require i 2 c packets with 16-bit data payloads. communication with both classes of registers (i 2 c and fp-ram) is performed via i 2 c. the format of the i 2 c telegram depends on which type of register is being ad- dressed. 2.14.2. i 2 c bus interface the vpx has an i 2 c bus slave interface and uses i 2 c clock synchronization to slow down the interface if re- quired. the i 2 c bus interface uses one level of subad- dressing. first, the bus address selects the ic, then a subaddress selects one of the internal registers. fp controller read address write address data status i 2 c subaddress space fp-ram fig. 2 ? 39: fp register addressing 00 ff 17f the i 2 c interface of the vpx conforms to the i 2 c bus specification for the fast-mode. it incorporates slope control for the falling edges of the sda and scl signals. if the power supply of the vpx is switched off, both pins scl and sda float. external pull-up devices must be adapted to fulfill the required rise time for the fast-mode. for bus loads up to 200 pf, the pull-up device could be a resistor; for bus loads between 200 pf and 400 pf, the pull-up device can be a current source (3 ma max.) or a switched resistor circuit. 2.14.3. reset and i 2 c device address selection the vpx can respond to one of two possible chip ad- dresses. the address selection is made at reset by an externally supplied level on the oe pin. this level is latched on the inactive going edge of res . table 2 ? 15: i 2 c bus device addresses oe a6 a5 a4 a3 a2 a1 a0 r/w hex 0 1 0 0 0 0 1 1 1/0 86/87 1 1 0 0 0 1 1 1 1/0 8e/8f 2.14.4. protocol description once the reset is complete, the ic is selected by assert- ing the device address in the address part of a i 2 c trans- mission. a device address pair is defined as a write ad- dress (86 hex or 8e hex) and a read address (87 hex or 8f hex). writing is done by sending the device write ad- dress first, followed by the subaddress byte and one or two data bytes. for reading, the read subaddress has to be transmitted, first, by sending the device write address (86 hex or 8e hex) followed by the subaddress, a second start condition with the device read address (87 hex or 8f hex), and reading one or two bytes of data. it is not al- lowed to send a stop condition in between. this will re- sult in reading erratic data. the registers of the vpx have 8 or 16 bit data size; 16-bit registers are accessed by reading/writing two 8-bit data bytes with the high byte first. the order of the bits in a data/address/subaddress byte is always msb first. figure 2 ? 40 shows i 2 c bus protocols for read and write operations of the interface; the read operation requires an extra start condition after the subaddress and repeti- tion of the read chip address, followed by the read data bytes. the following protocol examples use device ad- dress hex 86/87.
preliminary data sheet vpx 3225d, vpx 3224d 36 micronas write to hardware control registers s 1 0 0 0 0 1 1 0 ack sub-addr ack send data-byte ack p read from hardware control registers s 1 0 0 0 0 1 1 0 ack sub-addr ack s 1 0 0 0 0 1 1 1 ack receive data-byte nak p note: s = i 2 c-bus start condition p = i 2 c-bus stop condition ack = acknowledge-bit (active low on sda from receiving device) nak = no acknowledge-bit (inactive high on sda from receiving device) fig. 2 ? 40: i 2 c bus protocol (msb first) sda scl 1 0 sp 2.14.5. fp control and status registers due to the internal architecture of the vpx, the ic cannot react immediately to all i 2 c requests which interact with the embedded processor (fp). the maximum response timing is appr. 20 ms (one tv field) for the fp processor if tv standard switching is active. if the addressed pro- cessor is not ready for further transmissions on the i 2 c bus, the clock line scl is pulled low. this puts the cur- rent transmission into a wait state called clock synchro- nization. after a certain period of time, the vpx releases the clock and the interrupted transmission is carried on. before accessing the address or data registers for the fp interface (fprd, fpwr, fpdat), make sure that the busy bit of fp is cleared (fpsta). write to fp s 1 0 0 0 0 1 1 0 ack fpwr ack send fp-address- byte high ack send fp-address- byte low ack p s 1 0 0 0 0 1 1 0 ack fpdat ack send data-byte high ack send data-byte low ack p read from fp s 1 0 0 0 0 1 1 0 ack fprd ack send fp-address- byte high ack send fp-address- byte low ack p s 1 0 0 0 0 1 1 0 ack fpdat ack s 1 0 0 0 0 1 1 1 ack receive data-byte high ack receive data-byte low nak p
vpx 3225d, vpx 3224d preliminary data sheet 37 micronas 2.15. initialization of the vpx 2.15.1. power-on-reset in order to completely specify the operational mode of the vpx, appropriate values must be loaded into the i 2 c and fp registers. after powering the vpx, an internal power-on-reset clears all the fp/i 2 c-registers. an ini- tialization routine loads the default values for both the i 2 c and fp registers from internal program rom. the external res pin forces all outputs to be tri-stated. at the inactive going edge of the res pin, oe and field are read in for configuration. the field pin is internally pulled down, an external pull-up resistor could be used to define a different power-on configuration. the power- on configuration is read on every rising edge of the exter- nal res pin. either inactive (tri-state) or active output pins could be chosen with the field pin at the inactive going edge of res . in the inactive state, all relevant output pins are tri- stated, this includes port a, port b, href, vref, field, vact, pixclk, llc, and llc2. in the active setup, all of these pins are driven. table 2 ? 16 gives an overview of the different setups. additionally, the data ports a and b can be tri-stated with an external pullup resistor at the output enable pin oe . the ports can be reactivated ei- ther by the oe pin or via setting bit 7 in i 2 c register 0xf2 ( ? oeq_dis ? ). the vpx always comes up in ntsc square pixel mode (640x240, both fields). in the case of inactive low power mode, the internal h-sync scheduler is switched off, as in normal low power mode. after enabling the chip via i 2 c interface, the h-sync scheduler is enabled and the chips goes into a normal active ntsc operation condi- tion. 2.15.2. software reset the vpx provides the possibility of a software reset gen- erated via i 2 c command (i 2 c register 0xaa, bit 2). be aware that this software reset does not activate the con- figuration read-in during power-on reset. 2.15.3. low power mode the vpx goes into low power mode, if the inactive mode has been chosen. this is equal to the manual chosen low-power mode. note, that every manual selection of the power mode (full or low-power) overwrites (resets!) the power-up configuration. however, the current con- figuration cannot be read via the corresponding i 2 c reg- ister. other restrictions are that the selection of the low- power mode limits the rate of the i 2 c-interface to 100 khz, and that the ic comes up with full power con- sumption until the low-power circuit becomes active. table 2 ? 16: state of the pins during and after reset pins reset active inactive setup (field=0) active setup (field=1) port a tri-state tri-state active (oe =0) port b tri-state tri-state active (oe =0) href tri-state tri-state active vref tri-state tri-state active field pull down tri-state active vact tri-state tri-state active pixclk tri-state tri-state active 13.5 mhz llc tri-state tri-state active 27 mhz tdo/ llc2 tri-state tri-state active program- mable output with the field pin pulled down at the inactive going edge of res , the vpx comes up in the low power mode. this mode is introduced for power consumption critical applications. it can be turned on and off with bit[1:0] in the i 2 c register 0xaa ( ? lowpow ? ). there are three levels of low power mode. when any of them is turned on, the vpx waits for at least one complete video scan line in or- der to complete all internal tasks and then goes into tris- tate mode. the exact moment is not precisely defined, so care should be taken to deactivate the system using vpx data before the end of the video scan line in which the vpx is switched into low power mode. during the low power mode, all the i 2 c and fp registers are preserved, so that the vpx restores its normal operation as soon as low power mode is turned off, without need for any re-ini- tialization. on the other hand, all the i 2 c and fp regis- ters can be read/written as usual. the only exception is the third level (value of 3 in i 2 c register 0xaa) of low power. in that mode, i 2 c speeds above 100 kbit/sec are not allowed. in modes 1 and 2, i 2 c can be used up to the full speed of 400 kbit/s.
preliminary data sheet vpx 3225d, vpx 3224d 38 micronas 2.16. jtag boundary-scan, test access port (tap) the design of the test access port, which is used for boundary-scan test, conforms to standard ieee 1149.1-1990, with one exception. also included is a list of the mandatory instructions supported, as well as the optional instructions. the following comprises a brief overview of some of the basics, as well as any optional features which are incorporated. the ieee 1149.1 docu- ment may be necessary for a more concise description. finally, an adherence section goes through a checklist of topics and describes how the design conforms to the standard. the implementation of the instructions highz and clamp conforms to the supplement p1149.1/d11 (oc- tober 1992) to the standard 1149.1-1990. 2.16.1. general description the tap in the vpx is incorporated using the four signal interface. the interface includes tck, tms, tdi, and tdo. the optional treset signal is not used. this is not needed because the chip has an internal power-on- reset which will automatically steer the chip into the test-logic-reset state. the goal of the interface is to provide a means to test the boundary of the chip. there is no support for internal or bist(built-in self test). the one exception to ieee 1149.1 is that the tdo output is shared with the llc2 signal. this was necessitated due to i/o restrictions on the chip (see section 2.16.3. ? exceptions to ieee 1149.1 ? for more information). 2.16.2. tap architecture the tap function consists of the following blocks: tap- controller, instruction register, boundary-scan register, bypass register, optional device identification register, and master mode register. 2.16.2.1. tap controller the tap controller is responsible for responding to the tck and tms signals. it controls the transition between states of this device. these states control selection of the data or instruction registers, and the actions which occur in these registers. these include capture, shifting, and update. see fig. 5 ? 1 of ieee 1149.1 for tap state diagram. 2.16.2.2. instruction register the instruction register chooses which one of the data registers is placed between the tdi and tdo pins when the select data register state is entered in the tap con- troller. when the select instruction register state is ac- tive, the instruction register is placed between the tdi and tdo. instructions the following instructions are incorporated: ? bypass ? sample/preload ? extest ? master mode ? id code ? highz ? clamp 2.16.2.3. boundary scan register the boundary scan register (bsr) consists of boundary scan cells (bscs) which are distributed throughout the chip. these cells are located at or near the i/o pad. it al- lows sampling of inputs, controlling of outputs, and shift- ing between each cell in a serial fashion to form the bsr. this register is used to verify board interconnect. input cell the input cell is constructed to achieve capture only. this is the minimal cell necessary since internal test (intest) is not supported. the cell captures either the system input in the capture-dr state or the previous cells output in the shift-dr state. the captured data is then available to the next cell. no action is taken in the update-dr state. see figure 10 ? 11 of ieee 1149.1 for reference. output cell the output cell will allow both capture and update. the capture flop will obtain system information in the cap- ture-dr state or previous cells information in the shift-dr state. the captured data is available to the next cell. the captured or shifted data is downloaded to the update flop during the update-dr state. the data from the update flop is then multiplexed to the system output pin when the extest instruction is active. other- wise, the normal system path exists where the signal from the system logic flows to the system output pin. see fig. 10 ? 12 of ieee 1149.1 for reference.
vpx 3225d, vpx 3224d preliminary data sheet 39 micronas tristate cell each group of output signals, which are tristatable, is controlled by a boundary scan cell (output cell type). this allows either the normal system signal or the scanned signal to control the tristate control. in the vpx, there are four such tristate control cells which control groups of output signals (see section ? output driver tris- tate control ? for further information). bidirect cell the bidirect cell is comprised of an input cell and a tris- tate cell as described in the ieee standard. the signal pixclk is a bidirectional signal. 2.16.2.4. bypass register this register provides a minimal path between tdi and tdo. this is required for complicated boards where many chips may be connected in serial. 2.16.2.5. device identification register this is an optional 32-bit register which contains the micronas identification code (jedec controlled), part and revision number. this is useful in providing the tes- ter with assurance that the correct part and revision are inserted into a pcb. 2.16.2.6. master mode data register this is an optional register used to control an 8-bit test register in the chip. this register supports shift and up- date. no capture is supported. this was done so the last word can be shifted out for verification. 2.16.3. exception to ieee 1149.1 there is one exception to ieee 1149.1. the exception is to paragraphs 3.1.1.c., 3.5.1.b, and 5.2.1.d (test- logic-reset state). because of pin limitations on the chip, a pin is shared for two functions. when the circuit is in the test-logic-reset state, the llc2 signal is driven out the tdo/llc2 pin. when the circuit leaves the test-logic-reset state, the tdo signal is driven on this line. as long as the circuit is not in the test-log- ic-reset state, all the rules for application of the tdo signal adhere to the ieee1149.1 spec. since the vpx uses the jtag function as a boundary- scan tool, the vpx does not sacrifice test of this pin since it is verified by exercising jtag function. the designer of the pcb must make careful note of this fact, since he will not be able to scan into chips receiving the llc2 sig- nal via the vpx. the pcb designer may want to put this chip at the end of the chain or bring the vpx tdo out separately and not have it feed another chip in a chain. 2.16.4. ieee 1149.1-1990 spec adherence this section defines the details of the ieee1149.1 de- sign for the vpx. it describes the function as outlined by ieee1149.1, section 12.3.1. the section of that docu- ment is referenced in the description of each function. 2.16.4.1. instruction register (section 12.3.1.b.i of ieee 1149.1-1990) the instruction register is three bits long. no parity bit is included. the pattern loaded in the instruction register during capture-ir is binary ? 101 ? (msb to lsb). the two lsbs are defined by the spec to be ? 01 ? (bit 1 and bit 0) while the msb (bit 2) is set to ? 1 ? . 2.16.4.2. public instructions (section 12.3.1.b.ii of ieee 1149.1-1990) a list of the public instructions is as follows: instruction code (msb to lsb) extest 000 sample/preload 001 id code 010 master mode 011 highz 100 clamp 110 bypass 100 ? 111 the extest and sample/preload instructions both apply the boundary scan chain to the serial path. the id code instruction applies the id register to the serial chain. the bypass, the highz, and the clamp instructions apply the bypass register to the serial chain. the master mode instruction is a test data instruction for public use. it provides the ability to control an 8-bit test register in the chip.
preliminary data sheet vpx 3225d, vpx 3224d 40 micronas 2.16.4.3. self-test operation (section 12.3.1.b.iii of ieee 1149.1-1990). there is no self-test operation included in the vpx de- sign which is accessible via the tap. 2.16.4.4. test data registers (section 12.3.1.b.iv of ieee 1149.1-1990). the vpx includes the use of four test data registers. they are the required bypass and boundary scan regis- ters, the optional id code register, and the master mode register. the bypass register is, as defined, a 1-bit register ac- cessed by codes 100 through 111, inclusive. since the design includes the id code register, the bypass register is not placed in the serial path upon power-up or test- logic-reset. the master mode is an 8-bit test register which is used to force the vpx into special test modes. this is reset upon power-on-reset. this register supports shift and update only. it is not recommended to access this regis- ter. the loading of that register can drive the ic into an undefined state. 2.16.4.5. boundary scan register (section 12.3.1.b.v of ieee 1149.1-1990) the boundary scan chain has a length of 38 shift regis- ters. the scan chain order is specified in the section ? pin connections ? . 2.16.4.6. device identification register (section 12.3.1.b.vi of ieee 1149.1-1990) the manufacturer ? s identification code is ? 6c ? (hex) for micronas. the general implementation scheme uses only the 7 lsbs and excludes the msb, which is the par- ity bit. the part number is ? 7230 ? (hex) . in case of vpx 3225d and ? 7231 ? (hex) . in case of vpx 3224d. the version code starts from ? 1 ? (hex) and changes with every revision. the version number relates to changes of the chip interface only. 2.16.4.7. performance (section 12.3.1.b.vii of ieee 1149.1-1990) see section ? specification ? for further information. version part number manufacturer id 31 28 27 12 11 1 0 1 0001010001101000000000001101 00 1 7f 87 272300d9 fig. 2 ? 41: device identification register
vpx 3225d, vpx 3224d preliminary data sheet 41 micronas tap state transitions select data reg capture dr shift dr exit1 dr pause dr exit2 dr update dr select instr. reg capture ir shift ir exit1 ir pause ir exit2 ir update ir run / idle test-logic-reset tdo active tdo inactive $0 $1 $2 $3 $4 $5 $6 $7 $8 $9 $a $b $c $d $e $f 1 0 0 0 0 00 0 00 0 0 0 0 tms=0 tms=0 11 11 11 11 11 11 tms=1 tms=1 1 state code state transitions are dependend on the value of tms, synchronized by tck. tdo could be used as programmable output pin or llc2 clock signal (see pin description). fig. 2 ? 42: tap state transitions
preliminary data sheet vpx 3225d, vpx 3224d 42 micronas ?? ************************************************************* ?? ?? this is the bsdl for the 44-pin version of the vpxd design. ?? ?? ************************************************************* library ieee; use work.std_1149_1_1990.all; entity vpxd_44 is generic (physical_pin_map:string := ? undefined ? ); port( ?? define ports tdi,tck,tms: in bit; tdo,href,vref,field: out bit; a: out bit_vector(7 downto 0); pvdd,pvss: linkage bit; pixclk: out bit; oeq: in bit; llc, vact: out bit; b: out bit_vector(7 downto 0); sda,scl: inout bit; vss,xtal2,xtal1,vdd: linkage bit; resq: in bit; avdd,avss,vrt,isgnd: linkage bit; cin,vin1,vin2,vin3: in bit ); attribute pin_map of vpxd_44 : entity is physical_pin_map; constant package_44 : pin_map_string := ?? map pins to signals ? tdi : 1 ? & ? tck : 2 ? & ? tdo : 3 ? & ? href : 4 ? & ? vref : 5 ? & ? field : 6 ? & ? a : (7,8,9,10,14,15,16,17) ? & ? pvdd : 11 ? & ? pixclk : 12 ? & ? pvss : 13 ? & ? oeq : 18 ? & ? llc : 19 ? & ? vact : 20 ? & ? b : (21,22,23,24,25,26,27,28), ? & ? sda : 29 ? & ? scl : 30 ? & ? resq : 31 ? & ? vss : 32 ? & ? vdd : 33 ? & ? xtal2 : 34 ? & ? xtal1 : 35 ? & ? avdd : 36 ? & ? cin : 37 ? & ? avss : 38 ? & ? vin1 : 39 ? & ? vin2 : 40 ? & ? vrt : 41 ? & ? vin3 : 42 ? & ? isgnd : 43 ? & ? tms : 44 ? ; attribute tap_scan_in of tdi : signal is true; ?? define jtag controls attribute tap_scan_mode of tms : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_clock of tck : signal is (10.0e6,both); ?? max frequency and levels tck can be stopped at. attribute instruction_length of vpxd_44: entity is 3; ?? define instr. length attribute instruction_opcode of vpxd_44: entity is ? extest (000), ? & ?? external test
vpx 3225d, vpx 3224d preliminary data sheet 43 micronas ? sample (001), ? & ?? sample/preload ? idcode (010), ? & ?? id code ? mastermode (011), ? & ?? master mode (internal test) ? highz (100), ? & ?? highz ? clamp ? (110), ? & ?? clamp ? bypass (100,101,110,111), ? ; ?? bypass attribute register_access of vpxd_44: entity is ?? instr. vs register ? boundary (extest,sample), ? & ?? control ? bypass (bypass, highz, clamp), ? & ? idcode[32] (idcode), ? & ? mastermode[8] (mastermode) ? ; attribute instruction_capture of vpxd_44: entity is ? 101 ? ; ?? captured instr. attribute idcode_register of vpxd_44: entity is ? 0001 ? & ?? initial rev ? 0100011010000000 ? & ?? part numb. 7230 ? 0000 ? & ?? 7f count ? 1101100 ? & ?? micronas code ? parity ? 1 ? ; ?? mandatory lsb attribute boundary_cells of vpxd_44: entity is ? bc_1,bc_4 ? ; ? -bc_1 for output cell ?? bc_4 for input cell attribute boundary_length of vpxd_44: entity is 38; ?? boundary scan length attribute boundary_register of vpxd_44: entity is ?? boundary scan defin. ?? num cell port function safe ccel disval rslt ? 37 (bc_4, vin3, input, x ), ? & ? 36 (bc_4, vin2, input, x ), ? & ? 35 (bc_4, vin1, input, x ), ? & ? 34 (bc_4, cin, input, x ), ? & ? 33 (bc_1, *, internal, x ), ? & ?? low power mode ? 32 (bc_4, resq, input, x ), ? & ? 31 (bc_4, scl, input, x ), ? & ? 30 (bc_1, scl, output3, x, 30, 1, z ), ? & ?? open collector ? 29 (bc_4, sda, input, x ), ? & ? 28 (bc_1, sda, output3, x, 28, 1, z ), ? & ?? open collector ? 27 (bc_1, b(0), output3, x, 19, 1, z ), ? & ? 26 (bc_1, b(1), output3, x, 19, 1, z ), ? & ? 25 (bc_1, b(2), output3, x, 19, 1, z ), ? & ? 24 (bc_1, b(3), output3, x, 19, 1, z ), ? & ? 23 (bc_1, b(4), output3, x, 19, 1, z ), ? & ? 22 (bc_1, b(5), output3, x, 19, 1, z ), ? & ? 21 (bc_1, b(6), output3, x, 19, 1, z ), ? & ? 20 (bc_1, b(7), output3, x, 19, 1, z ), ? & ? 19 (bc_1, *, control, x ), ? & ?? control ? 18 (bc_1, vact, output3, x, 16, 1, z ), ? & ? 17 (bc_1, llc, output3, x, 16, 1, z ), ? & ? 16 (bc_1, *, control, x ), ? & ?? control ? 15 (bc_4, oeq, input, x ), ? & ? 14 (bc_1, a(0), output3, x, 8, 1, z ), ? & ? 13 (bc_1, a(1), output3, x, 8, 1, z ), ? & ? 12 (bc_1, a(2), output3, x, 8, 1, z ), ? & ? 11 (bc_1, a(3), output3, x, 8, 1, z ), ? & ? 10 (bc_1, *, control, x ), ? & ?? control ? 9 (bc_1, pixclk,output3, x, 10, 1, z ), ? & ? 8 (bc_1, *, control, x ), ? & ?? control ? 7 (bc_1, a(4), output3, x, 8, 1, z ), ? & ? 6 (bc_1, a(5), output3, x, 8, 1, z ), ? & ? 5 (bc_1, a(6), output3, x, 8, 1, z ), ? & ? 4 (bc_1, a(7), output3, x, 8, 1, z ), ? & ? 3 (bc_1, *, control, x, , 1, z ), ? & ?? control ? 2 (bc_1, field, output3, x, 3, 1, z ), ? & ? 1 (bc_1, vref, output3, x, 16, 1, z ), ? & ? 0 (bc_1, href, output3, x, 16, 1, z ), ? ; end vpxd_44;
preliminary data sheet vpx 3225d, vpx 3224d 44 micronas 2.17. enable/disable of output signals in order to enable the output pins of the vpx to achieve the high impedance/tristate mode, various controls have been implemented. the following paragraphs give an overview of the different tristate modes of the output sig- nals. it is valid for all output pins, except the xtal2 (which is the oscillator output) and the vrt pin (which is an analog reference voltage). bs (boundary scan) mode: the tristate control by the test access port tap for boundary scan has the highest priority. even if the tap- controller is in the extest or clamp mode, the tristate behavior is only defined by the state of the different boundary scan registers for enable control. if the tap controller is in highz mode, then all output pins are in tristate mode independently of the state of the different boundary scan registers for enable control. reset state: if the tap-controller is not in the extest mode, then the reset-state defines the state of all digital outputs. the only exception is made for the data output of the bound- ary scan interface tdo. if the circuit is in reset condition (res = 0), then all output interfaces are in tristate mode. i 2 c control: the tristate condition of groups of signals can also be controlled by setting the i 2 c-register 0xf2. if the circuit is neither in extest mode nor reset state, then the i 2 c-register 0xf2 defines whether the output is in tris- tate condition or not (see ? i 2 c-registers vpx back- end ? ). output enable input oe : the output enable signal oe only effects the video out- put ports. if the previous three conditions do not cause the output drivers to go into high impedance mode, then the oe signal defines the driving conditions of the video data ports. the oe pin function can be disabled via i 2 c register 0xf2 [oeq_dis]. the oe signal will either directly con- nect the output drivers or it will be latched internally with the llc signal depending on i 2 c register 0xf2 [latoeq]. additionally, a delay of 1 llc clock cycle can be enabled with i 2 c register 0xf2 [oeqdel]. table 2 ? 17: output driver configuration extest reset i 2 c oe# driver stages active ? ? ? output driver stages are defined by the state of the different boundary scan enable registers. inactive active ? ? output drivers are in high impedance mode. inactive inactive = 0 ? output drivers are in high impedance mode. pixclk is working. inactive inactive = 1 = 0 output drivers href, vref, field, vact, llc, are working. outputs a[7:0] and b[7:0] are working inactive inactive = 1 = 1 output drivers href, vref, field, vact, llc, are working. output drivers of a[7:0] and b[7:0] are in high impedance mode. remark: extest mode is an instruction conforming to the standard for boundary scan test ieee 1149.1 ? 1990
vpx 3225d, vpx 3224d preliminary data sheet 45 micronas 3. specification 3.1. outline dimensions fig. 3 ? 1: 44-pin plastic leaded chip carrier package (plcc44) weight approximately 2.5 g dimensions in mm 16.5 0.1 ? video data output 8 a6 out nc port a ? video data output 9 a5 out nc port a ? video data output 10 a4 out nc port a ? video data output 11 pvdd supply x supply voltage pad circuits 12 pixclk out nc pixel clock output 13 pvss supply x ground, pad circuits 14 a3 out nc port a ? video data output
preliminary data sheet vpx 3225d, vpx 3224d 46 micronas pin connections and short descriptions, continued pin no. pin name type connection short description plcc44 (if not used) 15 a2 out nc port a ? video data output 16 a1 out nc port a ? video data output 17 a0 out nc port a ? video data output 18 oe in vss output ports enable input 19 llc out nc pixclk * 2 = 27 mhz output 20 vact out nc active video qualifier output 21 b7 out nc port b ? video data output 22 b6 out nc port b ? video data output 23 b5 out nc port b ? video data output 24 b4 out nc port b ? video data output 25 b3 out nc port b ? video data output 26 b2 out nc port b ? video data output 27 b1 out nc port b ? video data output 28 b0 out nc port b ? video data output 29 sda in/out nc i 2 c bus data 30 scl in/out nc i 2 c bus clock 31 res in x reset input 32 vss supply x ground, digital circuitry 33 vdd supply x supply voltage, digital circuitry 34 xtal2 osc out x analog crystal output 35 xtal1 osc in x analog crystal input 36 avdd supply x supply voltage, analog circuitry 37 cin ain nc analog chroma input 38 avss supply x ground, analog circuitry 39 vin1 ain nc analog video 1 input 40 vin2 ain nc analog video 2 input 41 vrt reference x reference voltage top, video adc 42 vin3 ain nc analog video 3 input 43 isgnd supply x signal ground, analog video inputs 44 tms in nc boundary-scan-test mode select
vpx 3225d, vpx 3224d preliminary data sheet 47 micronas 3.3. pin descriptions pins 44, 1 ? jtag input pins, tms, tdi (fig. 3 ? 4) test mode select and test data input signals of the jtag test access port (tap). both signals are inputs with a ttl compatible input specification. to comply with jtag specification they use pull-ups at their input stage. the input stage of the tms and tdi uses a ttl schmitt trigger. pin 2 ? jtag input pin, tck (fig. 3 ? 3) clock signal of the test-access port. it is used to syn- chronize all jtag functions. when jtag operations are not being performed, this pin should be driven to vss. the input stage of the tck uses a ttl schmitt trigger. pin 3 ? jtag output pin, tdo, llc2, dact (fig. 3 ? 6) data output for jtag test access port (tap). moreover, if test access port (tap) is in test-logic-reset state, this pin can be used as output pin of the llc2 clock sig- nal (i 2 c reg. 0xf2 bit[4] = 1) or it can be used as output pin for the active vbi-data signal dact (see section 2.13.). pins 4 to 6 ? reference signals, href, vref, field (fig. 3 ? 6) these signals are internally generated sync signals. the state of field during the positive edge of res selects the power up mode (see section 2.15.1.). pins 7 to 10, 14 to 17 ? video, port a[7:0] (fig. 3 ? 6) video output port to deliver luma and/or chroma data. pin 11 ? supply voltage (pad circuitry), pvdd pins 12, 19 ? pixel clock, pixclk , llc (fig. 3 ? 6) pixclk and llc are the reference clock signals for the video data transmission ports a[7:0] and b[7:0]. pin 13 ? ground (pad circuitry), pvss pin 18 ? output enable input signal, oe (fig. 3 ? 3) the output enable input signal has ttl schmitt trigger input characteristic. it controls the tri-state condition of both video ports. the state during the positive edge of res selects the i 2 c device address (see section 2.14.3.). pins 20 ? video qualifier output, vact (fig. 3 ? 6) this pin delivers a signal which qualifies active video samples. pins 21 to 28 ? video, port b[7:0] (fig. 3 ? 6) video output port to deliver chroma data. in 8-bit modes, port b can be activated as programmable output (see section 2.6.3.). pin 29 ? i 2 c bus data, sda (fig. 3 ? 5) this pin connects to the i 2 c bus data line. pin 30 ? i 2 c bus clock, scl (fig. 3 ? 5) this pin connects to the i 2 c bus clock line. pin 31 ? reset input, res (fig. 3 ? 3) a low level on this pin resets the vpx 3225d. pin 32 ? ground (digital circuitry), vss pin 33 ? supply voltage (digital circuitry), vdd pins 34, 35 ? crystal input and output, xtal1 , xtal2 (fig. 3 ? 8) these pins are connected to a 20.25 mhz crystal oscilla- tor which is digitally tuned by integrated shunt capaci- tances. an external clock can be fed into xtal1. in this case, clock frequency adjustment must be switched off. pin 36 ? supply voltage (analog circuitry), avdd pin 37 ? chroma input, cin (fig. 3 ? 12, fig. 3 ? 11) this pin is connected to the s-vhs chroma signal. a re- sistive divider is used to bias the input signal to the middle of the converter input range. cin can only be connected to the chroma (video 2) a/d converter. the signal must be ac-coupled. pin 38 ? ground (analog front-end), avss pins 39, 40, 42 ? video input 1 ? 3, vin1 ? 3 (fig. 3 ? 10) these are the analog video inputs. a cvbs, s-vhs luma signal is converted using the luma (video 1) a/d converter. the vin1 input can also be switched to the chroma (video 2) adc. the input signal must be ac- coupled. pin 41 ? reference voltage top, vrt (fig. 3 ? 9) via this pin, the reference voltage for the a/d converters is decoupled. the pin is connected with 10 f/47 nf to the signal ground pin. pin 43 ? ground (analog signal input), isgnd this is the high-quality ground reference for the video input signals.
preliminary data sheet vpx 3225d, vpx 3224d 48 micronas 3.4. pin configuration 7 8 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 38 39 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 4443424140 vpx 3225d top view vin1 avss cin avdd xtal1 xtal2 vdd vss res scl sda b0 b1 b2 b3 b4 b5 vin2 vrt vin3 isgnd tms tdi tck tdo (llc2, dact) href vref pvss a2 a1 a0 a3 pixclk pvdd a4 a5 a6 a7 field oe llc vact b7 b6 vpx 3224d fig. 3 ? 2: 44-pin plcc package. 3.5. pin circuits fig. 3 ? 3: tck, oe , res pin vss vdd fig. 3 ? 4: tms, tdi pvdd pin vss vdd fig. 3 ? 5: i 2 c interface sda, scl pin vss vdd the characteristics of the schmitt triggers are depend on the supply of vdd/vss. fig. 3 ? 6: a[7:0], b[7:0], href, vref, llc, pixclk, vact, tdo out pin
vpx 3225d, vpx 3224d preliminary data sheet 49 micronas fig. 3 ? 7: reference signal field and wake-up selection lowpow on positve edge of res field pin vss vdd avdd avss p n 0.5m fig. 3 ? 8: crystal oscillator xtal2 xtal1 f eclk avss avdd p + ? bias adc reference fig. 3 ? 9: reference voltage vrt vrt avdd avss to adc1 fig. 3 ? 10: video inputs adc1 vin1 n n n vin2 vin3 clamping fig. 3 ? 11: video inputs adc2 to adc2 vin1 n n cin avdd avss bias vrt fig. 3 ? 12: unselected video inputs vin1, vin2, vin3, cin
preliminary data sheet vpx 3225d, vpx 3224d 50 micronas 4. electrical characteristics 4.1. absolute maximum ratings symbol parameter pin name min. max. unit t a ambient temperature 0 65 ? 40 125 ? 0.3 6 v p tot max power dissipation due to package characteristics vdd, pvdd, avdd 1170 mw input voltage of field, tms, tdi pvss ? 0.5 pvdd + 0.5 1) v input voltage tck pvss ? 0.5 6 v input voltage sda, scl vss ? 0.5 6 v signal swing a[7:0], b[7:0], pixclk, href, vref, field, vact, llc, tdo pvss ? 0.5 pvdd + 0.5 1) v maximum | vdd ? avdd | 0.5 v maximum | vss ? pvss | maximum | vss ? avss | maximum | pvss ? avss | 0.1 v 1) external voltage exceeding pvdd+0.5 v should not be applied to these pins even when they are tri-stated. stresses beyond those listed in the ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the ? recommended operating conditions/characteristics ? of this specification is not implied. exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability.
vpx 3225d, vpx 3224d preliminary data sheet 51 micronas 4.2. recommended operating conditions symbol parameter pin name min. typ. max. unit t a ambient operating temperature ? 0 ? 65 ? 1). 4.2.1. recommended analog video input conditions symbol parameter pin name min. typ. max. unit v vin analog input voltage vin1, vin2, vin3, cin 0 ? 3.5 v c cp input coupling capacitor video inputs vin1, vin2, vin3 680 nf c cp input coupling capacitor chroma input cin 1 nf r pd recommended drive impedance vin1, vin2, vin3, cin 75 100
preliminary data sheet vpx 3225d, vpx 3224d 52 micronas 4.2.2. recommended i 2 c conditions (timing diagram see fig. 5 ? 3 on page 61) symbol parameter pin name min. typ. max. unit v imil i 2 c-bus input low voltage scl, sda 0.3 vdd v imih i 2 c-bus input high voltage sda 0.6 vdd f scl i 2 c-bus frequency scl 100 khz t i2c1 i 2 c start condition setup time scl, sda 1200 ns t i2c2 i 2 c stop condition setup time sda 1200 ns t i2c3 i 2 c-clock low pulse time scl 5000 ns t i2c4 i 2 c-clock high pulse time 5000 ns t i2c5 i 2 c-data setup time before rising edge of clock scl, sda 55 ns t i2c6 i 2 c-data hold time after falling edge of clock 55 ns 4.2.3. recommended digital inputs levels of res , oe , tck, tms, tdi symbol parameter pin name min. typ. max. unit v il input voltage low res , oe , tck, tms, tdi ? 0.5 0 0.8 v v ih input voltage high res , oe , tck 2.0 5 6 v v ih input voltage high tdi, tms 2.0 pvdd pvdd + 0.3 v
vpx 3225d, vpx 3224d preliminary data sheet 53 micronas 4.2.4. recommended crystal characteristics symbol parameter min. typ. max. unit t a operating ambient temperature 0 ? 65 ? 20.250000 fundamental ? mhz f p /f p accuracy of adjustment ? ? f p /f p frequency temperature drift ? ? ? ? 25 c 0 shunt capacitance 3 ? 7 pf c 1 motional capacitance 20 ? 30 ff load capacitance recommendation c lext external load capacitance 1 ) from pins to ground (plcc44) (pin names: xtal1 xtal2) ? 4.7 ? pf dco characteristics 2) c icloadmin effective load capacitance @ min. dco-position, code 0, package: plcc44 3 4.3 5.5 pf c icloadrng effective load capacitance range, dco codes from 0..255 8.7 12.7 16.7 pf 1) remarks on defining the external load capacitance: external capacitors at each crystal pin to ground are required. they are necessary to tune the effective load capacitance of the pcbs to the required load capacitance (c l ) of the crystal. the higher the capacitors, the lower the clock frequency results. the nominal free running frequency should match f p = 20.25 mhz. due to different layouts of customer pcbs, the matching capacitor size should be determined in the application. the suggested value is a figure based on experience with various pcb layouts. tuning condition: code dvco register = ? 720 2) remarks on pulling range of dco: the pulling range of the dco is a function of the used crystal and effective load capacitance of the ic (c icload + c loadboard ). the resulting frequency (f l ) with an effective load capacitance of c leff = c icload + c loadboard is 1 + 0.5 * [ c 1 / (c 0 + c l ) ] f l = f p * ??????????????????????? 1 + 0.5 * [ c 1 / (c 0 + c leff ) ] 3) remarks on dco codes: the dco hardware register has 8 bits; the fp control register uses a range of ? 2048...2047.
preliminary data sheet vpx 3225d, vpx 3224d 54 micronas 4.3. characteristics at t a = 0 to 65 ? ? 45@3.3v 75@5 v p tot total power dissipation, normal operation condition avdd, vdd, pvdd 0.95 w p tot total power dissipation, low power mode avdd, vdd, pvdd 0.1 w 4.3.2. characteristics, reset symbol parameter min. typ. max. unit test conditions t res min res low pulse to initiate an internal reset 50 ns xtal osc. is working t res int internal reset hold time 3.2 ? 7) 1 ms xtal osc. is working c load (field) < 50 pf i leak < 10 a t s-wu setup time of pin field and oe to posedge of res 20 ns t h-wu hold time of pin field and oe to posedge of res 20 ns i pd pull-down current during res = 0 at pin field 42 75 68 a v field = 5v r pu recommended pull-up resistor to enforce a logical 1 to pin field 10 k 4.3.3. xtal input characteristics symbol parameter min. typ. max. unit test conditions v i clock input voltage, xtal1 1.3 v pp capacitive coupling of xtal1, xtal 2 remains open t startup1 oscillator startup time at vdd slew-rate of 1 v / 1 s k xtal duty cycle 50 %
vpx 3225d, vpx 3224d preliminary data sheet 55 micronas 4.3.4. characteristics, analog front-end and adcs symbol parameter pin name min. typ. max. unit test conditions v vrt reference voltage top vrt 2.5 2.61 2.72 v 10 f//10 nf, 1 g probe luma ? path r vin input resistance vin1, vin2 1 m code clamp ? dac = 0 c vin input capacitance vin2 , vin3 5 pf v vin full scale input voltage 1.86 1.93 2.0 v pp min. agc gain v vin full scale input voltage 0.5 0.6 0.7 v pp max. agc gain agc agc step width 0.145 0.163 0.181 db 6-bit resolution = 63 steps f i = 1 mhz dnl agc agc differential non-linearity ? 2 dbr of max. agc gain v vincl input clamping level, cvbs 1.0 v binary level = 68 lsb min. agc gain q cl clamping dac resolution ? 16 15 steps 6 bit ? i ? dac, bipolar v vin =15v i cl ? lsb input clamping current per step 0.7 1 1.3 a v vin = 1 . 5 v dnl icl clamping dac differential non-linearity ? path r cin input resistance svhs chroma cin, vin1 1.4 2.0 2.6 k c vin input capacitance cin, vin1 5 pf v cin full scale input voltage, chroma cin, vin1 1.08 1.14 1.2 v pp v cindc input bias level, svhs chroma vin1 ? 1.5 ? v binary code for open chroma input 128 dynamic characteristics for all video-paths (luma + chroma) bw bandwidth vin1, vin2 10 14 mhz ? 2 dbr input signal level xtalk crosstalk, any two video inputs vin2 , vin3, cin ? 56 ? 48 db 1 mhz, ? 2 dbr signal level thd total harmonic distortion cin ? 48 ? 45 db 1 mhz, 5 harmonics, ? 2 dbr signal level sinad signal to noise and distortion ratio 42 46 db 1 mhz, all outputs, ? 2 dbr signal level inl integral non-linearity, ? 12 dbr, 4.4 mhz signal on dc ram p dp differential phase 1.5 deg dc - ramp
preliminary data sheet vpx 3225d, vpx 3224d 56 micronas 4.3.5. characteristics, control bus interface (timing diagram see fig. 5 ? 3 on page 61) symbol parameter pin name min. typ. max. unit test conditions v imol output low voltage sda, scl ? ? 0.4 0.6 v v i l = 3 ma i l = 6 ma t imol1 i 2 c-data output hold time after falling edge of clock scl sda 15 ns t imol2 i 2 c-data output setup time be- fore rising edge of clock scl sda 100 ns f scl = 1 mhz, vdd = 5 v t f signal fall time sda, scl ? ? 300 ns c l = 400 pf, r pu = 4,7 k f scl clock frequency 1) scl 0 ? 100 1000 khz khz low power mode normal operating condition 1) the maximum clock frequency of the i2c interface is limited to 100 khz while the ic is working in the low power mode. 4.3.6. characteristics, jtag interface (test access port tap) (timing diagram see fig. 5 ? 5 on page 63) symbol parameter min. typ. max. unit test conditions cycl-tap jtag cycle time 100 ns h-tap tck high time 50 ns l-tap tck low time 50 ns v res-tap minimum supply voltage to initiate an internal reset of the jtag-tap generated by a voltage supply supervision circuit 3.5 v vdd pin test access port (tap), see timing diagram (fig. 5 ? 5 on page 63) t s-tap tms, tdi setup time 12 ns t h-tap tms, tdi hold time 12 ns t d-tap tck to tdo propagation delay for valid data 50 ns t on-tap tdo turn-on delay 45 ns t off-tap tdo turn-off delay 45 ns boundary-scan test, characteristics of all io pins which are connected to the boundary scan register chain t s-pins input signals setup time at capture-dr 10 ns t h-pins input signals hold time at capture-dr 10 ns t d-pins tck to output signals, delay for valid data 50 ns t on-pins turn-on delay 20 ns t off-pins turn-off delay 20 ns
vpx 3225d, vpx 3224d preliminary data sheet 57 micronas 4.3.7. characteristics, digital inputs/outputs symbol parameter min. typ. max. unit test conditions digital input pins tms, tdi, tck, res , oe , scl, sda c in input capacitance 5 8 pf i i input leakage current input pins tck, res , oe , scl, sda ? 1 +1 a v i = v ss v i ? 25 ? 55 +1 a v i = v ss v i ? pvdd v i o output leakage current ? 1 +1 a a while ic remains in low power mode v i = v ss v i llc llc duty cycle h / l + h ) 50 % t llc2 llc2 cycle time 74 ns llc2 llc2 duty cycle h / l + h ) 50 % t pixclk pixclk cycle time 74 ns pixclk pixclk duty cycle h / l + h ) 50 % t hclk1 output signal hold time for llc2 0 ns t dclk1 propagation delay for llc2 10 ns t hclk2 output signal hold time for pixclk 10 ns t dclk2 propagation delay for pixclk 18 ns
preliminary data sheet vpx 3225d, vpx 3224d 58 micronas 4.3.9. digital video interface symbol parameter min. typ. max. unit test conditions data and control pins (llc to a[7:0], b[7:0], href, vref, field, vact: the following timing specifications refer to the timing diagrams of section 5.7. on page 64. t oh output hold time 20 ns i 2 c reg. h ? aa ? bit[6]=1 t pd propagation delay 35 ns new llc output timing (available starting version d4) t oh output hold time 8 ns i 2 c reg. h ? aa ? bit[6]=0 t pd propagation delay 23 ns output enable by oe (for more information, see section 5.4. on page 62) t on output enable oe of a[7:0], b[7:0] 15 ns t off output disable oe of a[7:0], b[7:0] 15 ns t on1 output enable oe of a[7:0], b[7:0] 5 ns t off1 output disable oe of a[7:0], b[7:0] 5 ns oe input timing t su input data set-up time 11 ns t hd input data hold time 3 ns 4.3.10. characteristics, ttl output driver output pins a[7:0], b[7:0], pixclk, llc, vact, href, vref, field, tdo/llc2 symbol parameter min. typ. max. unit test conditions t ra rise time 2 5 10 ns c l = 30 pf, strength = 4 t fa fall time 2 5 10 ns c l = 30 pf, strength = 4 i oh (0) output high current (strength = 0) ? 1.37 ? 2.25 ? 2.87 ma v oh = 0.6 v i ol (0) output low current (strength = 0) 1.75 3.5 4.5 ma v oh = 2.4 v i oh (7) output high current (strength = 7) ? 11 ? 18 ? 25 ma v oh = 0.6 v i ol (7) output low current (strength = 7) 14 28 36 ma v oh = 2.4 v
vpx 3225d, vpx 3224d preliminary data sheet 59 micronas 4.3.10.1. ttl output driver description the driving capability/strength is controlled by the state of the two i 2 c registers f8 hex and f9 hex . a special pvdd, pvss supply is used only to support the digital output pins. this means, inherently, that in case of tri-state conditions, external sources should not drive these signals above the voltage pvdd which sup- plies the output pins. all timing specifications are based on the following as- sumptions: ? the load capacitance of the fast pins (output driver ty- pe a) is c a = 30 pf, ? the load capacitance of the remaining pins (output driver type b) is c b = 50 pf, ? no static currents are assumed, ? the driving capability of the pads is str = 4, which means that 5 of 8 output drivers are enabled. the typical case specification relates to: ? the ambient temperature is t a = 25 ? the power supply of the pad circuits is pvdd = 3.3 v, and the power supply of the digital parts is vdd = 5.0 v. the best case specification relates to: ? a junction temperature of t j = 0 ? the power supply of the pad circuits is pvdd = 3.6 v, and the power supply of the digital parts is vdd = 5.25 v. the worst case specification relates to: ? a junction temperature of t j = 125 ? the power supply of the pad circuits is pvdd = 3.0 v, and the power supply of the digital parts is vdd = 4.75 v. rise times are specified as a transition between 0.6 v to 2.4 v. fall times are defined as a transition between 2.4 v to 0.6 v. strength 0 strength 1 strength 2 strength 3 strength 4 strength 5 strength 6 strength = 7 fig. 4 ? 1: block diagram of the output stages note: the drivers of the output pads are implemented as a parallel connection of 8 tri-state buffers of the same size. the buffers are enabled depending on the desired driver strength. this opportunity offers the ad- vantage of adapting the driver strength to on-chip and off-chip constraints, e.g. to minimize the noise result- ing from steep signal transitions.
preliminary data sheet vpx 3225d, vpx 3224d 60 micronas 5. timing diagrams 5.1. power-up sequence the reset should not reach high level before the oscillator has started. this requires a reset delay of >1 ms (see fig.5 ? 1). t startup1 supplies crystal oscillator 95% v ioh res fig. 5 ? 1: power-up sequence t startup2 5.2. default wake-up selection the state of field and oe pins are sampled at the high (inactive) going edge of res in order to select between two power-on parameters. oe determines the i 2 c ad- dress. the field pin is internally pulled down. an external pull- up resistor defines a different power on configuration. field defines the global wake-up mode of the vpx. with field pulled down, the vpx goes into low power mode. res field v ioh v iol v ioh v iol fig. 5 ? 2: default wake-up selection t s-wu t h-wu oe t res min
vpx 3225d, vpx 3224d preliminary data sheet 61 micronas 5.3. control bus timing diagram scl sda as input sda as output f im t i2c3 t i2c1 t i2c5 t i2c6 t i2c2 t imol2 t imol1 t i2c4 fig. 5 ? 3: i 2 c bus timing diagram (data: msb first)
preliminary data sheet vpx 3225d, vpx 3224d 62 micronas 5.4. output enable by pin oe oe signals a[7:0], b[7:0] t off t on fig. 5 ? 4: drive control by oe input oe signals a[7:0], b[7:0] t su t su synchronizing the oe signal with clock llc: controlled by i 2 c register ? oena ? h ? f2 bit[5] oeqdel = 1 latoeq = 0 latoeq = 1 t off1 t on1 signals a[7:0], b[7:0] t off1 t on1
vpx 3225d, vpx 3224d preliminary data sheet 63 micronas 5.5. timing of the test access port tap t off-tap t on-tap cycl h-tap l ? tap t h-tap t s-tap t d-tap tck tdi, tms tdo fig. 5 ? 5: timing of test access port tap 5.6. timing of all pins connected to the boundary-scan-register-chain t off-pins t on-pins t h-pins t s-pins t d-pins tck inputs outputs fig. 5 ? 6: timing with respect to input and output signals
preliminary data sheet vpx 3225d, vpx 3224d 64 micronas 5.7. timing diagram of the digital video interface 2.4 v 1.5 v 0.6 v t oh a[7:0], b[7:0] t pd 2.4 v 1.5 v 0.6 v clock output llc fig. 5 ? 7: video output interface (detailed timing) href, vref, field, vact t llc 5.7.1. characteristics, clock signals 2.4 v 1.5 v 0.6 v t fa t llc llc pixclk t ra 2.4 v 1.5 v 0.6 v llc2 fig. 5 ? 8: clocks: llc, llc2, pixclk (detailed timing) t hclk2 t dclk2 t hclk2 t dclk2 2.4 v 1.5 v 0.6 v t hclk1 t dclk1 t hclk1 t dclk1
vpx 3225d, vpx 3224d preliminary data sheet 65 micronas 6. control and status registers the following tables give definitions for the vpx control and status registers. the number of bits indicated for each register in the table is the number of bits imple- mented in the hardware, i.e. a 9-bit register must always be accessed using two data bytes, but the 7 msb will be ? 0 ? on write operations and don ? t care on read opera- tions. write registers that can be read back are indicated in the mode column. the control register modes are ? w write-only register ? r read-only register ? w/r write/read register ? d register is double latched ? v register is latched with vsync default values are initialized at reset. the mnemonics used in the micronas vpx demo software are given in the last column. 6.1. overview i 2 c-registers address hex number of bits mode function group name h ? 00 8 r manufacture id chip ident. jedec h ? 01 h ? 02 8 8 r 16-bit part number chip ident. partnum h ? 03 8 r jedec2 chip ident. jedec2 h ? 35 8 r fp status fp interface fpsta h ? 36 16 w fp read fp interface fprd h ? 37 16 w fp write fp interface fpwr h ? 38 16 w/r fp data fp interface fpdat h ? aa 8 w low power mode, llc mode output llc h ? b3 8 r soft error counter byte slicer softerrcnt h ? b4 8 r sync status sync slicer sync_stat h ? b5 8 r hsync counter sync slicer sync_cnt h ? b6 8 r read filter coefficient bit slicer coeff_rd h ? b7 8 r read data slicer level bit slicer level_rd h ? b8 h ? b9 h ? ba 8 8 8 w w w clock run-in and framing code don ? t care mask high clock run-in and framing code don ? t care mask mid clock run-in and framing code don ? t care mask low byte slicer mask h ? bb h ? bc h ? bd 8 8 8 w w w clock run-in and framing code reference high clock run-in and framing code reference mid clock run-in and framing code reference low byte slicer reference h ? c0 8 w soft slicer level bit slicer soft_slicer h ? c1 h ? c2 8 8 w w ttx bitslicer frequency lsb ttx bitslicer frequency msb bit slicer ttx_freq h ? c5 8 w filter coefficient bit slicer coeff h ? c6 8 w data slicer level bit slicer data_slicer h ? c7 8 w accumulator mode bit slicer accu h ? c8 8 w sync slicer level sync slicer sync_slicer h ? c9 8 w standard byte slicer standard h ? ce 8 w bit error tolerance byte slicer tolerance h ? cf 8 w byte count byte slicer byte_cnt h ? f2 8 w output enable output oena h ? f8 8 w pad driver strength ? ttl output pads type a output driver_a h ? f9 8 w pad driver strength ? ttl output pads type b output driver_b
preliminary data sheet vpx 3225d, vpx 3224d 66 micronas fp-ram address hex number of bits mode function group name h ? 12 12 r/w general purpose control status gp_ctrl h ? 13 12 r standard recognition status status asr h ? 15 12 r vertical field counter status vcnt h ? 20 12 w standard select stand. sel. sdt h ? 21 12 w input select stand. sel. insel h ? 22 12 w start point of active video stand. sel. sfif h ? 23 12 w luma/chroma delay adjust stand. sel. ldly h ? 30 12 w acc reference level to adjust c r , c b levels on picture bus color proc. accref h ? 31 12 r measured burst amplitude status bampl h ? 32 12 w acc multiplier value for secam db chroma comp. to adjust c b on pict. bus color proc. accb h ? 33 12 w acc multiplier value for secam dr chroma comp. to adjust c r on pict. bus color proc. accr h ? 39 12 w amplitude killer level color proc. kilvl h ? 3a 12 w amplitude killer hysteresis color proc. kilhy h ? 74 12 r measured sync amplitude value status sampl h ? cb 12 r number of lines per field, p/s: 312, n: 262 status nlpf h ? dc 12 w ntsc tint angle, 512 = ? f0 12 r software version number status version h ? f7 12 w/r crystal oscillator line-locked mode, dvco xlck h ? f8 12 w crystal oscillator center frequency adjust dvco dvco h ? f9 12 r crystal oscillator center frequency adjustment value dvco adjust h ? 10f 12 r delay of vact relative to href during window 1 readtab1 vact_dly1 h ? 11f 12 r delay of vact relative to href during window 2 readtab2 vact_dly2 h ? 120 12 w vertical begin winloadtab1 vbegin1 h ? 121 12 w vertical lines in / temporal decimation / field select winloadtab1 vlinesin1 h ? 122 12 w vertical lines out winloadtab1 vlinesout1 h ? 123 12 w horizontal begin winloadtab1 hbeg1 h ? 124 12 w horizontal length winloadtab1 hlen1 h ? 125 12 w number of pixels winloadtab1 npix1 h ? 126 12 w selection for peaking / coring winloadtab1 peaking1 h ? 127 12 w brightness winloadtab1 brightness1 h ? 128 12 w contrast / noise shaping / clamping winloadtab1 contrast1 h ? 12a 12 w vertical begin winloadtab2 vbegin2 h ? 12b 12 w vertical lines in winloadtab2 vlinesin2 h ? 12c 12 w vertical lines out winloadtab2 vlinesout2 h ? 12d 12 w horizontal begin winloadtab2 hbeg2 h ? 12e 12 w horizontal length winloadtab2 hlen2 h ? 12f 12 w number of pixels winloadtab2 npix2 h ? 130 12 w selection for peaking / coring winloadtab2 peaking2 h ? 131 12 w brightness winloadtab2 brightness2
vpx 3225d, vpx 3224d preliminary data sheet 67 micronas fp-ram name group function mode number of bits address hex h ? 132 12 w contrast winloadtab2 contrast2 h ? 134 12 w start line even field vbi-window start_even h ? 135 12 w end line even field vbi-window end_even h ? 136 12 w start line odd field vbi-window start_odd h ? 137 12 w end line odd field vbi-window end_odd h ? 138 12 w control vbi-window vbi-window vbicontrol h ? 139 12 w slicer data size vbi-window slsize h ? 140 12 w r register for control and latching controlword h ? 141 12 r internal status register, do not overwrite infoword h ? 150 12 w format selection / shuffler / pixclk-mode formatter format_sel h ? 151 12 w start position of the programmable ? video active ? hvref pval_start h ? 152 12 w end position of the programmable ? video active ? hvref pval_stop h ? 153 12 w length and polarity of href, vref, field hvref refsig h ? 154 12 w output multiplexer / multi-purpose output output mux. outmux h ? 157 12 w number of frames to output within 3000 frames temp. decim. tdecframes
preliminary data sheet vpx 3225d, vpx 3224d 68 micronas 6.1.1. description of i 2 c control and status registers table 6 ? 1: i 2 c-registers vpx front-end i 2 c-registers vpx front-end address hex number of bits mode function default name fp interface h ? 35 8 r fp status bit [0] write request bit [1] read request bit [2] busy fpsta h ? 36 16 w fp read bit [8:0] 9-bit fp read address bit [11:9] reserved, set to zero fprd h ? 37 16 w fp write bit [8:0] 9-bit fp write address bit [11:9] reserved, set to zero fpwr h ? 38 16 w/r fp data bit [11:0] fp data register, reading/writing to this register will autoincrement the fp read/ write address. only 16 bit of data are transferred per i 2 c telegram. fpdat table 6 ? 2: i 2 c-registers vpx back-end i 2 c-registers vpx back-end address hex number of bits mode function default name chip identification h ? 00 8 r manufacture id in accordance with jedec solid state products engineering council, washington dc micronas code ec hex jedec h ? 01 h ? 02 8 8 r r 16 bit part number (01: lsbs, 02: msbs) vpx 3225d 7230 hex ; vpx 3224d 7231 hex partnum partlow parthigh h ? 03 8 r jedec2 jedec2 bit [0] : ifield ifield bit [7:1] : reserved (must be treated don ? t care)
vpx 3225d, vpx 3224d preliminary data sheet 69 micronas i 2 c-registers vpx back-end name default function mode number of bits address hex output h ? f8 8 w pad driver strength ? ttl output pads typ a driver_a bit [2:0] : driver strength of port a[7:0] stra1 bit [5:3] : driver strength of pixclk, llc, and vact stra2 bit [7:6] : additional pixclk driver strength strength = bit [5:3] | {bit [7:6], 0} stra3 h ? f9 8 w pad driver strength ? ttl output pads typ b driver_b bit [2:0] : driver strength of port b[7:0] strb1 bit [5:3] : driver strength of href, vref, field, and llc2 strb2 bit [7:6] : reserved (must be set to zero) h ? f2 8 w output enable oena direct bit [0] : 1 enable video port a 0 disable / high impedance mode aen direct bit [1] : 1 enable video port b 0 disable / high impedance mode ben direct bit [2] : 1 enable pixclk output 0 disable / high impedance mode clken direct bit [3] : 1 enable href, vref, field, vact, llc, llc2 0 disable / high impedance mode zen direct bit[4] 1 enable llc2 to tdo pin (if jtag interface is in test-logic-reset state) 0 disable llc2 llc2en direct bit [5] : 1 no delay of oeq input signal 0 1 llc cycle delay of oeq input signal (if bit [6] = 1) oeqdel direct bit [6] : 1 latch oeq input signal with rising edge of llc 0 don ? t latch oeq input signal latoeq direct bit [7] : 1 disable oeq pin function oeq_dis h ? aa 8 w low power mode, llc mode llc bit [1:0] : low power mode 00 active mode, outputs enabled 01 outputs tri-stated; clock divided by 2, i 2 c full speed 10 outputs tri-stated; clock divided by 4, i 2 c full speed 11 outputs tri-stated; clock divided by 8, i 2 c < 100 kbit/s lowpow bit [2] : i 2 c reset iresen bit [3] : 1 connect llc2 to tdo pin 0 connect bit[4] to tdo pin llc2 bit [4] : if bit[3] then bit[4] defines llc2 polarity else bit[4] is connected to tdo pin llc2_pol bit [5] : switch-off slicer (if slowpow = 1 then all slicer registers are reset). slowpow bit [6] : 1 use old llc timing with long hold time 0 use new llc timing with shorter hold time (version d4 only) oldllc bit [7] : reserved (must be set to zero)
preliminary data sheet vpx 3225d, vpx 3224d 70 micronas table 6 ? 3: i 2 c-registers vpx slicer i 2 c-registers vpx slicer address hex number of bits mode function default name sync slicer h ? c8 8 w sync slicer bit [6:0] : binary sync slicer level is compared with binary data (0 ? b4 8 r sync status bit [5:0] : reserved (must be read don ? t care) bit [6] : 0 vert. window reset at line 624/524 (pal/ntsc) 1 vert. retrace set at line 628/528 (pal/ntsc) bit [7] : 0 field 2 reset at line 313/263 (pal/ntsc) 1 field 1 set at line 624/524 (pal/ntsc) sync_stat vwin field h ? b5 8 r hsync counter bit [7:0] : number of detected horizontal sync pulses per frame / 4 sync is detected within horizontal window of hpll counter is latched with vertical sync the register can be read at any time sync_cnt bit slicer h ? c0 8 w soft slicer bit [6:0] : binary soft slicer level is compared with abs[data] ( ? 128 ? c1 h ? c2 8 8 w w ttx bitslicer frequency lsb ttx bitslicer frequency msb bit [10:0] : freq = 2 11 * bitfreq / 20.25mhz = 702 for wst pal = 579 for wst ntsc or nabts = 506 for vps or wss = 102 for caption = 627 for antiope = 183 for time code bit [11] : 0 phase inc = freq 1 phase inc = freq*(1+1/8) before framing code phase inc = freq*(1+1/16) after framing code bit [15:12] :reserved (must be set to zero) 702 1 0 ttx_freql ttx_freqh ttx_freq ttx_phinc h ? c5 8 w filter coefficient bit [5:0] : high pass filter coefficient in 2 ? s complement 100000 = not allowed 100001 = ? 31 000000 = 0 011111 = +31 bit [7:6] : reserved (must be set to zero) 7 filter coeff h ? c6 8 w data slicer bit [7:0] : binary data slicer level is compared with abs[data] ( ? 128
vpx 3225d, vpx 3224d preliminary data sheet 71 micronas i 2 c-registers vpx slicer name default function mode number of bits address hex h ? c7 8 w accumulator mode bit [0] : 0 no action 1 reset dc and ac and flt accu (one shot) bit [1] : 0 dc accu enable 1 dc accu disable bit [2] : 0 ac and flt accu enable 1 ac and flt accu disable (only for vps and caption and wss line) bit [3] : 0 soft error correction enable 1 soft error correction disable bit [4] : 0 ac adaption disable 1 ac adaption enable bit [5] : 0 flt adaption disable 1 flt adaption enable bit [7:6] : reserved (must be set to zero) 0 0 1 0 1 1 accu reset dcen acen soften acaden fltaden h ? b6 8 r read filter coefficient coeff_rd h ? b7 8 r read data slicer level level_rd byte slicer h ? b3 8 r soft error counter bit [7:0] : counts number of soft error corrected bytes counter stops at 255 reset after read soft_cnt h ? c9 8 w standard bit [0] : 0 ttx disable 1 ttx enable bit [1] : 0 pal mode 1 ntsc mode bit [2] : 0 full field disable 1 full field enable bit [3] : 0 vps line 16 disable 1 vps line 16 enable bit [4] : 0 wss line 23 disable 1 wss line 23 enable bit [5] : 0 caption line 21 field 1 disable 1 caption line 21 field 1 enable bit [6] : 0 caption line 21 field 2 disable 1 caption line 21 field 2 enable bit [7] : 0 horizontal quit signal enable 1 horizontal quit signal disable 1 0 0 1 1 0 0 0 standard ttx ntsc full vps wss caption1 caption2 disquit h ? bd h ? bc h ? bb 8 8 8 w w w clock run-in and framing code reference low clock run-in and framing code reference mid clock run-in and framing code reference high bit [23:0] : clock run-in and framing code reference (lsb corresponds to first transmitted bit) h ? 55 h ? 55 h ? 27 reference h ? ba h ? b9 h ? b8 8 8 8 w w w clock run-in and framing code don ? t care mask low clock run-in and framing code don ? t care mask mid clock run-in and framing code don ? t care mask high bit [23:0] : clock run-in and framing code don ? t care mask (lsb corresponds to first transmitted bit) h ? 00 h ? 00 h ? 00 mask h ? ce 8 w bit error tolerance bit [1:0] : maximum number of bit errors in low mask bit [3:2] : maximum number of bit errors in mid mask bit [5:4] : maximum number of bit errors in high mask bit [7:6] : reserved (must be set to zero) 1 1 1 tolerance h ? cf 8 w output mode bit [5:0] : number of data bytes per text line including framing code bit [6] : 0 64 byte mode disable 1 64 byte mode enable bit [7] : 0 data output only for text lines 1 data output for every video line 43 1 0 out_mode byte_cnt fill64 dump
preliminary data sheet vpx 3225d, vpx 3224d 72 micronas 6.1.2. description of fp control and status registers table 6 ? 4: fp-ram vpx front-end fp-ram vpx front-end address hex number of bits mode function default name standard selection h ? 20 12 w standard select: bit [2:0] standard 0 pal b,g,h,i (50 hz) 4.433618 1 ntsc m (60 hz) 3.579545 2 secam (50 hz) 4.286 3 ntsc44 (60 hz) 4.433618 4 pal m (60 hz) 3.575611 5 pal n (50 hz) 3.582056 6 pal 60 (60 hz) 4.433618 7 ntsc comb (60 hz) 3.579545 bit [3] 0/1 mod standard modifier pal modified to simple pal ntsc modified to compensated ntsc secam modified to monochrome 625 ntscc modified to monochrome 525 bit [5:4] reserved; must be set to zero bit [6] 0/1 s-vhs mode off/on option bits allow to suppress parts of the initialization: bit [7] no hpll setup bit [8] no vertical setup bit [9] no acc setup bit [10] reserved, set to zero bit [11] status bit, write 0. after the fp has switched to a new standard, this bit is set to 1 to indicate operation complete. 0 sdt pal ntsc secam ntsc44 palm paln pal60 ntscc sdtmod svhs sdtopt h ? 21 12 w input select: writing to this register will also initialize the standard. bit [1:0] luma selector 00 vin3 01 vin2 10 vin1 11 reserved bit [2] chroma selector 0/1 vin1/cin bit [4:3] if compensation 00 off 01 6 db/okt 10 12 db/okt 11 10 db/mhz only for secam bit [6:5] chroma bandwidth selector 00 narrow 01 normal 10 broad 11 wide bit [7] 0/1 adaptive/fixed secam notch filter bit [8] 0/1 enable luma lowpass filter bit [10:9] hpll speed 00 no change 01 terrestrial 10 vcr 11 mixed bit [11] status bit, write 0; this bit is set to 1 to indicate operation complete. 00 1 00 01 insel vis cis ifc cbw fntch lowp hpllmd h ? 22 12 w picture start position, this register sets the start point of active vid- eo. this can be used e.g. for panning. the setting is updated when ? sdt ? register is updated 0 sfif h ? 23 12 w luma/chroma delay adjust, the setting is updated when ? sdt ? register is updated bit [5:0] reserved, set to zero bit [11:6] luma delay in clocks, allowed range is +1 ... ? 7 0 ldly
vpx 3225d, vpx 3224d preliminary data sheet 73 micronas fp-ram vpx front-end name default function mode number of bits address hex color processing h ? 30 12 w acc reference level to adjust c r , c b levels on picture bus. a value of 0 disables the acc, chroma gain can be adjusted via accb / accr register. the setting is updated when ? sdt ? register is updated. p/n: 2070 s: 0 accref h ? 32 12 w acc multiplier value for secam db chroma component to adjust c b level on picture bus. the setting is updated when ? sdt ? register is updated. b [10:0] eeemmmmmmmm m * 2 ? e s: 1155 accb h ? 33 12 w acc multiplier value for secam dr chroma component to adjust c r level on picture bus. the setting is updated when ? sdt ? register is updated. b [10:0] eeemmmmmmmm m * 2 ? e s: 1496 accr h ? 39 12 w amplitude killer level (0: killer disabled) 25 kilvl h ? 3a 12 w amplitude killer hysteresis 5 kilhy h ? dc 12 w ntsc tint angle, 512 = ? f8 12 w crystal oscillator center frequency adjust, ? 2048 ... 2047 ? 720 dvco h ? f9 12 r crystal oscillator center frequency adjustment value for line-locked mode, true adjust value is dvco ? adjust. for factory crystal alignment, using standard video signal: set dvco = 0, set lock mode, read crystal offset from adjust register and use negative value for initial center frequency adjust- ment via dvco. adjust h ? f7 12 w/r crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 4095/0 locked/unlocked 0 xlck fp status register h ? 12 12 w/r general purpose control bits bit [2:0] reserved, do not change bit [3] vertical standard force bit [8:4] reserved, do not change bit [9] disable flywheel interlace bit [11:10] reserved, do not change to enable vertical free run mode set vfrc=1 and dflw=0 0 1 gp_ctrl vfrc dflw h ? 13 12 r automatic standard recognition status bit [0] 1 vertical lock bit [1] 1 horizontally locked bit [2] 1 no signal detected bit [3] 1 color amplitude killer active bit [4] 1 disable amplitude killer bit [5] 1 color ident killer active bit [6] 1 disable ident killer bit [7] 1 interlace detected bit [8] 1 no vertical sync detection bit [9] 1 spurious vertical sync detection bit [11:10] reserved asr h ? cb 12 r number of lines per field, p/s: 312, n: 262 nlpf h ? 15 12 w/r vertical field counter, incremented per field vcnt h ? 74 12 r measured sync amplitude value, nominal: 768 sampl h ? 31 12 r measured burst amplitude bampl h ? f0 12 r software version number bit [7:0] internal software revision number bit [11:8] software release x
preliminary data sheet vpx 3225d, vpx 3224d 74 micronas fp-ram vpx front-end name default function mode number of bits address hex macrovision detection (version d4 only) h ? 170 12 r status of macrovision detection mcv_status bit [0]: agc pulse detected bit [1]: pseudo sync detected h ? 171 12 w first line of macrovision detection window 6 mcv_start h ? 172 12 w last line of macrovision detection window 15 mcv_stop
vpx 3225d, vpx 3224d preliminary data sheet 75 micronas table 6 ? 5: fp-ram vpx back-end fp-ram vpx back-end address hex number of bits mode function default name read table for window #1 h ? 10f 12 r position of vact bit [11:1]: delay of vact relative to the trailing edge of href vact_delay1 load table for window #1 (winloadtab1) h ? 120 12 w vertical begin 12 bit [8:0]: vertical begin (first active video line within a field) min. line number for 625/50 standards: 7 min. line number for 525/60 standards: 10 max. line number: determined by current tv line standard vbeg1 bit [11:9]: reserved (must be set to zero) h ? 121 12 w vertical lines in 0 bit [8:0]: number of input lines determines the range between the first and the last active video line within a field; vbeg + vlinei should not exceed the max. number of lines determined by the current line standard (exceeding values will be corrected automatically) vlinei1 bit [9]: enable temporal decimation (0: off, 1: on) with temporal decimation enabled, only the number of frames selected in register h ? 157 (tdecframes) will be output within an interval of 3000 frames tdec1 bit [11:10]: field disable flags 11 window disabled 10 window enabled in odd fields only 01 window enabled in even fields only 00 window enabled in both fields h ? 122 12 w vertical lines out 0 bit [8:0]: number of output lines vlineout cannot be greater than vlinein (no interpolation); for vlineout < vlinein vertical compression via line dropping is applied vlineo1 bit [11:9]: reserved (must be set to zero) h ? 123 12 w horizontal begin 0 bit [10:0]: horizontal start of window after scaling (relative to npix) hbeg > 0 enables cropping on the left side of the window hbeg1 bit [11]: reserved (must be set to zero) h ? 124 12 w horizontal length 704 bit [10:0]: horizontal length of window after scaling (relative to npix) hbeg + hlen cannot exceed npix hlen1 bit [11]: reserved (must be set to zero) h ? 125 12 w number of pixels 704 bit [10:0]: number of active pixels for the full active line (after scaling) npix must be an even value within the range 32 ... 864 npix1 bit [11]: reserved (must be set to zero)
preliminary data sheet vpx 3225d, vpx 3224d 76 micronas fp-ram vpx back-end name default function mode number of bits address hex h ? 126 12 w selection for peaking/coring 0 peaking1 bit [1:0]: coring subtracts lsbs of the higher frequency part of the video signal 00: subtract 0 lsbs 01: subtract 1/2 lsb 10: subtract 1 lsb 11: subtract 2 lsbs bit [4:2]: peaking an implemented peaking filter supports sharpness control with up to eight steps: 000: no peaking 001: low peaking 111: high peaking bit [5]: bypass lowpass bit [6]: bypass skewfilter bit [7]: bypass skewfilter vact bit [8]: swapping of chroma values 0 cb-pixels first 1 cr-pixels first bit [11:9]: reserved (must be set to zero) h ? 127 12 w brightness 0 bit [7:0]: brightness level offset value added to the video samples brightness can be selected in 256 steps within the range ? 127 ... 128 (binary offset format): 0: ? 127 255: 128 brightness1 bit [11:8]: reserved (must be set to zero) h ? 128 12 w contrast 32 contrast1 bit [5:0]: contrast level linear scale factor for luminance (default = 1.0) [5] integer part [4:0] fractional part contr1 bit [7:6]: noise shaping control for 10-bit to 8-bit conversion (default: rounding) 00: 9-bit to 8-bit via 1-bit rounding 01: 9-bit to 8-bit via truncation 10: 9-bit to 8-bit via 1-bit accumulation 11: 10-bit to 8-bit via 2-bit accumulation noise1 bit [8]: contrast brightness: clamping level 0 clamping level = 32, 1 clamping level = 16 (should normally be set to 1) clamp1 bit [9]: bypass brightness adder bribyp1 bit [10]: bypass contrast multiplier conbyp1 bit [11]: reserved (must be set to zero)
vpx 3225d, vpx 3224d preliminary data sheet 77 micronas fp-ram vpx back-end name default function mode number of bits address hex read table for window #2 h ? 11f 12 r position of vact bit [11:1]: delay of vact relative to the trailing edge of href vact_delay2 load table for window #2 (winloadtab2) h ? 12a 12 w vertical begin 17 bit [8:0]: vertical begin (first active video line within a field) min. line number for 625/50 standards: 7 min. line number for 525/60 standards: 10 max. line number: determined by current tv line standard vbeg2 bit [11:9]: reserved (must be set to zero) h ? 12b 12 w vertical lines in 500 bit [8:0]: number of input lines determines the range between the first and the last active video line within a field; vbeg + vlinei should not exceed the max. number of lines determined by the current line standard (exceeding values will be corrected automatically) vlinei2 bit [9]: enable temporal decimation (0: off, 1: on) with temporal decimation enabled, only the number of frames selected in register h ? 157 (tdecframes) will be output within an interval of 3000 frames tdec2 bit [11:10]: field disable flags 11: window disabled 10: window enabled in odd fields only 01: window enabled in even fields only 00: window enabled in both fields h ? 12c 12 w vertical lines out 240 bit [8:0]: number of output lines vlineout cannot be greater than vlinein (no interpolation); for vlineout < vlinein vertical compression via line dropping is applied vlineo2 bit [11:9]: reserved (must be set to zero) h ? 12d 12 w horizontal begin 0 bit [10:0]: horizontal start of window after scaling (relative to npix) hbeg > 0 enables cropping on the left side of the window hbeg2 bit [11]: reserved (must be set to zero) h ? 12e 12 w horizontal length 640 bit [10:0]: horizontal length of window after scaling (relative to npix) hbeg + hlen can not exceed npix hlen2 bit [11]: reserved (must be set to zero) h ? 12f 12 w number of pixels 640 bit [10:0]: number of active pixels for the full active line (after scaling) npix must be an even value within the range 32 ... 864 npix2 bit [11]: reserved (must be set to zero)
preliminary data sheet vpx 3225d, vpx 3224d 78 micronas fp-ram vpx back-end name default function mode number of bits address hex h ? 130 12 w selection for peaking/coring 0 peaking2 bit [1:0]: coring subtracts lsbs of the higher frequency part of the video signal 00: subtract 0 lsbs 01: subtract 1/2 lsb 10: subtract 1 lsb 11: subtract 2 lsbs bit [4:2]: peaking an implemented peaking filter supports sharpness control with up to eight steps: 000: no peaking 001: low peaking 111: high peaking bit [5]: bypass lowpass bit [6]: bypass skewfilter bit [7]: bypass skewfilter vact bit [8]: swapping of chroma values 0 cb-pixels first 1 cr-pixels first bit [11:9]: reserved (must be set to zero) h ? 131 12 w brightness 0 bit [7:0]: brightness level offset value added to the video samples brightness can be selected in 256 steps within the range ? 127 ... 128 (binary offset format): 0: ? 127 255: 128 brightness2 bit [11:8]: reserved (must be set to zero) h ? 132 12 w contrast 32 contrast2 bit [5:0]: contrast level linear scale factor for luminance (default = 1.0) [5] integer part [4:0] fractional part contr1 bit [7:6]: noise shaping control for 10-bit to 8-bit conversion (default: rounding) 00: 9-bit to 8-bit via 1-bit rounding 01: 9-bit to 8-bit via truncation 10: 9-bit to 8-bit via 1-bit accumulation 11: 10-bit to 8-bit via 2-bit accumulation noise1 bit [8]: contrast brightness: clamping level 0 clamping level = 32, 1 clamping level = 16 (should normally be set to 1) clamp1 bit [9]: bypass brightness adder bribyp1 bit [10]: bypass contrast multiplier conbyp1 bit [11]: reserved (must be set to zero)
vpx 3225d, vpx 3224d preliminary data sheet 79 micronas fp-ram vpx back-end name default function mode number of bits address hex load table for vbi-window h ? 134 12 w start line even field determines the first line of the vbi-window within even fields (note that lines are counted relative to the whole frame!) 272 start_even h ? 135 12 w end line even field determines the last line of the vbi-window within even fields (note that lines are counted relative to the whole frame!) 283 end_even h ? 136 12 w start line odd field determines the first line of the vbi-window within odd fields 10 start_odd h ? 137 12 w end line odd field determines the last line of the vbi-window within odd fields 21 end_odd h ? 138 12 w control vbi-window 0 vbicontrol bit [0]: vbi-window enable the selected vbi-window is activated only if this flag is set 0: disable 1: enable vbien bit [1]: vbi mode two modes for the output of vbi-data are supported 0: raw data 1140 samples of the video input are given directly to the output 1: sliced data sliced teletext data (in a package of 64 bytes) vbimode bit [2]: vertical identification the valid vbi-lines defined by the vbi-window can either be marked as active or as blanked lines 0: active lines during vbi-window (vact enabled) 1: blanked lines during vbi-window (vact suppressed) vbiident bit [11]: update the settings for the vbi-window (settings will only be updated if this latch flag is set!) vbilatch h ? 139 12 w slicer data size (0 corresponds to default value 64) 0 slsize
preliminary data sheet vpx 3225d, vpx 3224d 80 micronas fp-ram vpx back-end name default function mode number of bits address hex control word h ? 140 12 w r register for control and latching control word w bit [1:0]: sync timing mode 00 open mode horizontal and vertical sync are tracking the input signal 10 scan mode horizontal and vertical sync are free running 0 settm w bit [2]: mode for vact reference signal 0 length of vact corresponds to the size of the current window 1 programmable length of vact (for the whole field!) 0 vactmode w bit [4:3]: reserved (must be set to zero) 0 w bit [5]: latch window #1 1 latch (reset automatically) 1 latwin1 w bit [6]: latch window #2 1 latch (reset automatically) 1 latwin2 bit [9]: reserved (must be set to zero) 0 bit [10]: latch value for temporal decimation the number of frames for the temporal decimation is updated only if this flag is set 1 latch (reset automatically) 1 lattdec w bit [11]: latch timing modes selection of the timing mode is updated only if this flag is set 1 latch (reset automatically) 1 lattm info word h ? 141 12 r internal status register, do not overwrite this register can be used to query the current internal state due to the settings in the control word. infoword bit [2]: mode for vact reference signal 0 current window size 1 programmable size actvact bit [4:3]: reserved bit [11:8]: reserved
vpx 3225d, vpx 3224d preliminary data sheet 81 micronas fp-ram vpx back-end name default function mode number of bits address hex formatter h ? 150 12 w format selection format_sel bit [1:0]: format selector 00: yuv 4:2:2, itu-r601 01: yuv 4:2:2, itu-r656 10: yuv 4:2:2, bstream 0 format bit [2]: shuffler 0 port a = y, port b = uv 1 port a = uv, port b = y 0 shuf bit [3]: format of vbi-data (in itu-r656 mode only!) two possibilities are supported to disable the protected values 0 and 255: 0 limitation 1 7-bit resolution + odd parity lsb note that this selection is applied for lines within the vbi- window only! 0 range bit [4]: transmission of vbi-data (in itu-r656 mode only) 0 transmit as normal video data 1 transmit as ancillary data (with anc-header) 1 ancillary bit [5]: pixclk selection setting this bit activates the half-clock mode, in which pixclk is divided by 2 in order to spread the video data stream 0 full pixclk (normal operation) 1 pixclk divided by 2 0 halfclk bit [6]: disable splitting of text data bytes during normal operation, sliced teletext bytes are splitted into 2 nibbles and multiplexed to the luminance and chrominance part. setting this bit will disable this splitting. sliced teletext data will be output directly on the luminance path. note that the limitation of luminance data has to be disabled with bit [8]. the values 0 and 255 will no longer be protected in the luminance path! 0 splitdis bit [7]: reserved (must be set to zero) 0 bit [8]: disable limitation of luminance data (see bit [6]) 0 enabled 1 disabled 0 dislim bit [9]: suppress itu ? r656 headers for blank lines 0 hsup bit [10]: change of itu ? r656 header flags 0 change header flags in sav 1 change header flags in eav 0 flagdel bit [11]: reserved (must be set to zero) 0
preliminary data sheet vpx 3225d, vpx 3224d 82 micronas fp-ram vpx back-end name default function mode number of bits address hex hvref h ? 151 12 w start position of the programmable ? video active ? the start position has to be an even value and is given relative to the trailing edge of href. programmable vact is activated with bit [2] of the control word (h ? 140)! 40 pval_ start bit [10:0]: start of vact reference signal h ? 152 12 w end position of the programmable ? video active ? the end position has to be an even value and is given relative to the trailing edge of href. 720 pval_stop bit [10:0]: end of vact reference signal h ? 153 12 w href and vref control determines length and polarity of the timing reference signals refsig bit [0]: odd/even polarity 0 odd high 1 even high 0 oepol bit [1]: href polarity 0 active high 1 active low 0 hpol bit [2]: vref polarity 0 active high 1 active low 0 vpol bit [5:3]: vref pulse width, binary value + 2 000: pulse width = 2 111: pulse width = 9 0 vlen bit [6]: 1 disables field as output setting this bit will force the ? field ? pin to the high impedance state 0 disfield output multiplexer h ? 154 12 w output multiplexer 0 outmux bit [7:0]: multi-purpose bits on port b determines the state of port b when used as programmable output bmp bit [8]: activate multi-purpose bits on port b note that double clock mode has to be selected for this option! bmpon bit [9]: port mode 0 parallel_out, ? single clock ? , port a & b = fo[15:0]; 1 ? double clock ? port a = fo[15:8] / fo[7:0], port b = programmable output/not used; double bit [10]: switch ? vbi active ? qualifier 0 connect ? vbi active ? to vact pin 1 connect ? vbi active ? to tdo pin vbiact bit [11]: reserved (must be set to zero) temporal decimation h ? 157 12 w number of frames to output within 3000 frames this value will be activated only if the corresponding latch flag is set (control word h ? 140, bit [10] ). 3000 tdecframes
vpx 3225d, vpx 3224d preliminary data sheet 83 micronas 7. application notes 7.1. differences between vpx 3 220a and vpx 322xd the following items indicate the differences between the vpx 322xd and the vpx 3220a: internal ? the control registers (i 2 c and fp-ram) contain signif- icant changes. ? vpx 322xd incorporates a text slicer. furthermore, raw adc data is supported (sampling frequency of 20.25 mhz/8 bit, output data rate 13.5 mhz/16 bit). ? vpx 322xd does not support rgb and compressed video data output formats. the vpx 322xd supports itu-r601 and itu-r656. ? the vpx 322xd does not provide an asynchronous output mode, pixclk functions as an output only. the vpx 322xd supports half-clock data rate (6.75 mhz). ? the vpx 322xd does not provide a video data rate of 20.25 mhz at the output interface. ? the vpx 322xd has an implemented low power mode. external ? power-up default selection selection vpx 3220a vpx 322xd i 2 c device address pref oe wake-up default pads tristate/ active pixclk field ? the vpx 322xd does not use the internal i 2 c bus for power-up initialization. resultingly, the i 2 c interface will not be locked during that period. ? the vpx 322xd supports an 8-bit programmable out- put port if the device uses only a[7:0] for video data output. ? the vpx 322xd provides a href signal with a fixed low period, whereas the width of the high period will vary while the video input signal varies. 7.2. impact to signal to noise ratio fig. 7 ? 1 shows the impact of the variation of the power supply with respect to the snr of the adcs. the noise due to the digital output interface leads to an impact of the analog performance of the analog adcs. application engineers should minimize load capacitances and driver strength of the output signals. 38 39 40 41 42 43 44 45 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 snr [db] pvdd [v] fig. 7 ? 1: dependency between snr and power supply note: both adcs are working and routed to a[7:0], and b[7:0]. all interfaces are working with maximum driver strength bandwidth measurement is performed up to 5 mhz. 7.3. control interface 7.3.1. symbols < start condition > stop condition aa (sub-)address byte dd data byte 7.3.2. write data into i 2 c register <86 f2 dd> write to register oena 7.3.3. read data from i 2 c register <86 00 <87 dd> read manufacture id 7.3.4. write data into fp register <86 35 <87 dd> poll busy bit[2] until it is cleared <86 37 aa aa> write fp register write address <86 35 <87 dd> poll busy bit[2] until it is cleared <86 38 dd dd> write data into fp register 7.3.5. read data from fp register <86 35 <87 dd> poll busy bit[2] until it is cleared <86 36 aa aa> write fp register read address <86 35 <87 dd> poll busy bit[2] until it is cleared <86 38 <87 dd dd> read data from fp register
preliminary data sheet vpx 3225d, vpx 3224d 84 micronas 7.3.6. sample control code a windows api function set is provided for controlling the vpx. this api is independent of the actual used ver- sion of the vpx. it is recommended to control the vpx via this api, which allows flexible switching between dif- ferent vpx family members. the api is available on re- quest. the following code demonstrates the usage of the api to initialize the vpx. #include // vpxapi support header vpxinit(); // initializes the vpx from an ini file vpxsetvideosource(vpx_vin1, vpx_composite); vpxsetvideowindow(vpx_video_window1, 23, 288, 0, 720, 720, 3000, 0); vpxsetvideowindow(vpx_video_window2, 0, 0, 0, 0, 0, 0, 0); vpxsetvideowindow(vpx_vbi_window, 320, 336, 7, 23, 0, 0, 0); vpxsetvideostandard(vpx_pal); vpxsetvbimode(vpx_vbi_sliced_data, vpx_vbi_active); vpxsetvideoattribute(vpx_video_window1, vpx_contrast, 128); vpxsetvideoattribute(vpx_video_window1, vpx_brightness, 128); vpxsetvideoattribute(vpx_video_window1, vpx_saturation, 128); vpxsetvideoattribute(vpx_video_window1, vpx_hue, 128); vpxsetvideoattribute(vpx_video_window1, vpx_peaking, 128); vpxsetvideoattribute(vpx_video_window1, vpx_coring, 128); 7.4. xtal supplier name part no. country phone contact notes acal auremia 2351051 germany +49 (713) 15810 crystal holder hc49u lap tech xt1750 canada (905) 623 4101 bob parkins specify 13 pf load cap monitor product co. mm 49x ? 5297 usa (619) 433 ? 4510 mtron 5009 ? 359@20.25 usa (408) 257 ? 3399 george panos
vpx 3225d, vpx 3224d preliminary data sheet 85 micronas 7.5. typical application
preliminary data sheet vpx 3225d, vpx 3224d 86 micronas
vpx 3225d, vpx 3224d preliminary data sheet 87 micronas
preliminary data sheet vpx 3225d, vpx 3224d 88 micronas 8. data sheet history 1. preliminary data sheet: ? vpx 3225d, vpx 3224d video pixel decoders ? , edition march 5, 1997, 6251-432-1pd. first release of the preliminary data sheet. 2. preliminary data sheet: ? vpx 3225d, vpx 3224d video pixel decoders ? , edition nov. 9, 1998, 6251-432-2pd. second release of the preliminary data sheet. major changes: ? additional feature: macrovision detection ? format of itu-r656 ancillary data modified ? new timing for llc and oe pins ? section 3.1.: package outline dimensions changed micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-432-2pd all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. by this publication, micronas gmbh does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh.
micronas intermetall page 1 of 4 subject: data sheet concerned: supplement: edition: preliminary data sheet supplement new package for the vpx 3225dCc3, vpx 3224dCc3 1. the vpx 3225dCc3, vpx 3224dCc3 is also available in the pmqfp44 package. 2. the pinning of the pmqfp44 package has been changed, i.e. mirrored vertically. 3. production of the plcc44 package will continue. attachment: package information vpx 3225d, vpx 3224d new package for vpx 3225d, vpx 3224d vpx 3225d, vpx 3224d 6251-432-2pd, edition nov. 9, 1998 no. 6 / 6251-432-6pds april 8, 1999 vpx 3225d, vpx 3224d
vpx 3225d, vpx 3224d package information page 2 of 4 micronas intermetall 1. specifications 1.1. outline dimensions fig. 1C1: 44-pin plastic metric quad flat pack (pmqfp44) weight approx. 0.4 g dimensions in mm 1.2. pin connections and short descriptions nc = not connected; leave vacant lv = if not used, leave vacant x = obligatory pin no. pin name pin type connection (if not used) short description 1 vin1 ain nc analog video 1 input 2 avss supply x ground, analog circuitry 3 cin ain nc analog chroma input 4 avdd supply x supply voltage, analog circuitry 5 xtal1 osc in x analog crystal input 6 xtal2 osc out x analog crystal output 7 vdd supply x supply voltage, digital circuitry 8 vss supply x ground, digital circuitry 9 resq in x reset input 10 scl in/out nc i 2 c bus clock 11 sda in/out nc i 2 c bus data 12 b0 out nc port b - video data output 13 b1 out nc port b - video data output 14 b2 out nc port b - video data output d0024/2e 34 44 1 11 12 22 23 33 13.2 13.2 1.3 1.75 1.75 2.0 0.1 2.15 0.17 0.8 10 10 0.8 10 x 0.8 = 8 10 x 0.8 = 8 0.375
micronas intermetall page 3 of 4 package information vpx 3225d, vpx 3224d 15 b3 out nc port b - video data output 16 b4 out nc port b - video data output 17 b5 out nc port b - video data output 18 b6 out nc port b - video data output 19 b7 out nc port b - video data output 20 vact out nc active video qualifier output 21 llc out nc pixclk * 2 = 27 mhz output 22 oeq in vss output ports enable input 23 a0 out nc port a - video data output 24 a1 out nc port a - video data output 25 a2 out nc port a - video data output 26 a3 out nc port a - video data output 27 pvss supply x ground, pad circuits 28 pixclk out nc pixel clock output 29 pvdd supply x supply voltage pad circuits pin no. pin name pin type connection (if not used) short description
vpx 3225d, vpx 3224d package information page 4 of 4 micronas intermetall 1.3. pin configuration fig. 1C2: 44-pin pmqfp package 1.4. electrical characteristics 1.4.1. absolute maximum ratings stresses beyond those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions/characteristics of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. symbol parameter pin name min. max. unit t a ambient temperature 0 55 c t s storage temperature - 40 125 c t j junction temperature 0 125 c 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1234567891011 33 32 31 30 29 28 27 26 25 24 23 field vref href tdo (dact, llc2) tck tdi tms isgnd vin3 vrt vin2 oeq llc vact b7 b6 b5 b4 b3 b2 b1 b0 a6 a5 a4 pvdd pixclk a7 pvss a3 a2 a1 a0 avss cin avdd xtal1 xtal2 vin1 vdd vss resq scl sda vpx 3225d vpx 3224d

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